Texas Instruments TMS320DM643X DMP manual Purpose of the Peripheral, Features

Page 11

User's Guide

SPRU941A – April 2007

Ethernet Media Access Controller (EMAC)/

Management Data Input/Output (MDIO)

1Introduction

This document provides a functional description of the Ethernet Media Access Controller (EMAC) and physical layer (PHY) device Management Data Input/Output (MDIO) module integrated in the TMS320DM643x Digital Media Processor (DMP). Included are the features of the EMAC and MDIO modules, a discussion of their architecture and operation, how these modules connect to the outside world, and a description of the registers for each module.

The EMAC controls the flow of packet data from the system to the PHY. The MDIO module controls PHY configuration and status monitoring.

Both the EMAC and the MDIO modules interface to the system core through a custom interface that allows efficient data transmission and reception. This custom interface is referred to as the EMAC control module and is considered integral to the EMAC/MDIO peripheral.

1.1Purpose of the Peripheral

The EMAC module is used to move data between the DM643x device and another host connected to the same network, in compliance with the Ethernet protocol.

1.2Features

The EMAC/MDIO has the following features:

∙Synchronous 10/100 Mbps operation.

∙Standard Media Independent Interface (MII) to physical layer device (PHY).

∙EMAC acts as DMA master to either internal or external device memory space.

∙Eight receive channels with VLAN tag discrimination for receive quality-of-service (QOS) support.

∙Eight transmit channels with round-robin or fixed priority for transmit quality-of-service (QOS) support.

∙Ether-Stats and 802.3-Stats statistics gathering.

∙Transmit CRC generation selectable on a per channel basis.

∙Broadcast frames selection for reception on a single channel.

∙Multicast frames selection for reception on a single channel.

∙Promiscuous receive mode frames selection for reception on a single channel (all frames, all good frames, short frames, error frames).

∙Hardware flow control.

∙8K-byte local EMAC descriptor memory that allows the peripheral to operate on descriptors without affecting the CPU. The descriptor memory holds enough information to transfer up to 512 Ethernet packets without CPU intervention.

∙Programmable interrupt logic permits the software driver to restrict the generation of back-to-back interrupts, which allows more work to be performed in a single call to the interrupt service routine.

SPRU941A –April 2007Ethernet Media Access Controller (EMAC)/ 11

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Management Data Input/Output (MDIO)

 

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Contents Users Guide Submit Documentation Feedback Contents MAC Hash Address Register 1 MACHASH1 Appendix B Appendix aList of Figures Transmit Pacing Algorithm Test Register Tpacetest List of Tables Fifo Control Register Fifocontrol Field Descriptions Read This First Purpose of the Peripheral FeaturesEmac and Mdio Block Diagram Functional Block DiagramMemory Map Signal DescriptionsIndustry Standards Compliance Statement Clock ControlSignal Type Description Emac and Mdio SignalsField Bytes Description Ethernet Protocol OverviewEthernet Frame Format Ethernet Frame DescriptionPacket Buffer Descriptors Ethernet’s Multiple Access ProtocolProgramming Interface Typical Descriptor Linked List Basic Descriptor DescriptionTransmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Example 1. Transmit Buffer Descriptor in C Structure Format Transmit Buffer Descriptor FormatBuffer Length Next Descriptor PointerBuffer Pointer Buffer OffsetTeardown Complete Tdowncmplt Flag End of Packet EOP FlagOwnership Owner Flag End of Queue EOQ FlagReceive Buffer Descriptor Format Receive Buffer Descriptor Format#define Emacdscflagjabber Example 2. Receive Buffer Descriptor in C Structure FormatBuffer Length Jabber Flag Code Error Codeerror FlagAlignment Error Alignerror Flag CRC Error Crcerror FlagBus Arbiter Emac Control ModuleNo Match Nomatch Flag Internal MemoryMdio Module Components Mdio ModuleInterrupt Control Active PHY Monitoring PHY Register User AccessMdio Clock Generator Global PHY Detection and Link State MonitoringMdio Module Operational Overview Reading Data From a PHY Register Initializing the Mdio ModuleWriting Data To a PHY Register Example 3. Mdio Register Access Macros Example of Mdio Register Access CodeReceive Fifo Emac ModuleEmac Module Components Receive DMA EngineMAC Transmitter Clock and Reset LogicTransmit DMA Engine Transmit FifoReceive Inter-Frame Interval Media Independent Interface MIIData Reception Receive ControlIeee 802.3x-Based Receive Buffer Flow Control Collision-Based Receive Buffer Flow ControlInterpacket-Gap IPG Enforcement Transmit ControlCRC Insertion Adaptive Performance Optimization APOSpeed, Duplex, and Pause Frame Support Transmit Flow ControlReceive Address Matching Receive DMA Host ConfigurationPacket Receive Operation Receive Channel EnablingReceive Channel Teardown Hardware Receive QOS SupportHost Free Buffer Tracking Receive Frame Classification Promiscuous Receive ModeReceive Frame Treatment Receive Frame Treatment SummaryMiddle of Frame Overrun Treatment Receive OverrunMiddle of Frame Overrun Treatment Transmit Channel Teardown Transmit DMA Host ConfigurationPacket Transmit Operation Receive and Transmit LatencyTransfer Node Priority Reset ConsiderationsSoftware Reset Considerations Emac Control Module Initialization Hardware Reset ConsiderationsInitialization Enabling the EMAC/MDIO PeripheralExample 5. Mdio Module Initialization Code Example 4. Emac Control Module Initialization CodeMdio Module Initialization Emac Module Initialization Receive Packet Completion Interrupts Interrupt SupportEmac Module Interrupt Events and Requests Transmit Packet Completion InterruptsStatistics Interrupt Host Error InterruptProper Interrupt Processing User Access Completion InterruptMdio Module Interrupt Events and Requests Link Change InterruptEmulation Control Power ManagementEmulation Considerations Bit Field Emac Control Module Interrupt Control Register EwctlEmac Control Module Registers Acronym Register DescriptionEmac Control Module Interrupt Timer Count Register Ewinttcnt Mdio Version Register Version Field Descriptions Mdio Version Register VersionManagement Data Input/Output Mdio Registers Mdio Control Register Control Field Descriptions Mdio Control Register ControlPHY Link Status Register Link Field Descriptions PHY Acknowledge Status Register AlivePHY Link Status Register Link PHY Acknowledge Status Register Alive Field DescriptionsNo Mdio link change event Will clear the event and writing a 0 has no effect No Mdio user command complete event USERINTMASKED0 and USERINTMASKED1 correspond to USERACCESS0 WS-0 Userintmaskclear Mdio User Access Register 0 USERACCESS0 Field Descriptions Mdio User Access Register 0 USERACCESS0Bit Field Value Description Mdio User PHY Select Register 0 USERPHYSEL0Linksel Linkintenb PhyadrmonMdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User Access Register 1 USERACCESS1Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1Ethernet Media Access Controller Emac Registers Offset Acronym Register Description Ethernet Media Access Controller Emac RegistersNetwork Statistics Registers Offset Acronym Register DescriptionTransmit Control Register Txcontrol Field Descriptions Transmit Identification and Version Register TxidverTransmit Control Register Txcontrol Txtdnch Transmit Teardown Register TxteardownTransmit Teardown Register Txteardown Field Descriptions Receive Control Register Rxcontrol Field Descriptions Receive Identification and Version Register RxidverReceive Control Register Rxcontrol Rxtdnch Receive Teardown Register RxteardownReceive Teardown Register Rxteardown Field Descriptions TX7PEND Transmit Interrupt Status Unmasked Register TxintstatrawTransmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register TxintstatmaskedTX7MASK Transmit Interrupt Mask Set Register TxintmasksetTransmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register TxintmaskclearHostpend Statpend Rxpend Txpend MAC Input Vector Register MacinvectorMAC Input Vector Register Macinvector Field Descriptions Userint LinkintRX7PEND Receive Interrupt Status Unmasked Register RxintstatrawReceive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register RxintstatmaskedRX7MASK Receive Interrupt Mask Set Register RxintmasksetReceive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register RxintmaskclearHostpend Statpend MAC Interrupt Status Unmasked Register MacintstatrawMAC Interrupt Status Masked Register Macintstatmasked Hostmask MAC Interrupt Mask Set Register MacintmasksetMAC Interrupt Mask Clear Register Macintmaskclear Hostmask StatmaskRxpromch Rxpasscrc Rxqosen RxnochainRxcmfen Rxcsfen Rxcefen RxcafenFrames containing errors are filtered Receive multicast channel select RXCH7EN Receive Unicast Enable Set Register RxunicastsetReceive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register RxunicastclearReceive Maximum Length Register Rxmaxlen Field Descriptions Receive Maximum Length Register RxmaxlenReceive Buffer Offset Register Rxbufferoffset Reserved RX nFLOWTHRESH FFh RxfilterthreshReceive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol Field Descriptions MAC Control Register MaccontrolLoopback Sent. Full-duplex mode no outgoing pause frames are sentMAC Status Register Macstatus Field Descriptions MAC Status Register MacstatusBit Field Value Description MAC Status Register Macstatus Field DescriptionsFifo Control Register Fifocontrol Field Descriptions Emulation Control Register EmcontrolFifo Control Register Fifocontrol Emulation Control Register Emcontrol Field DescriptionsSoft Reset Register Softreset Field Descriptions MAC Configuration Register MacconfigSoft Reset Register Softreset MAC Configuration Register Macconfig Field DescriptionsMAC Source Address High Bytes Register Macsrcaddrhi MAC Source Address Low Bytes Register MacsrcaddrloMAC Hash Address Register 2 MACHASH2 Field Descriptions MAC Hash Address Register 1 MACHASH1MAC Hash Address Register 2 MACHASH2 MAC Hash Address Register 1 MACHASH1 Field DescriptionsBack Off Test Register Bofftest Field Descriptions Back Off Test Register BofftestTransmit Pacing Algorithm Test Register Tpacetest Transmit Pause Timer Register Txpause Field Descriptions Receive Pause Timer Register RxpauseTransmit Pause Timer Register Txpause Receive Pause Timer Register Rxpause Field DescriptionsMAC Address Low Bytes Register Macaddrlo Field Descriptions MAC Address Low Bytes Register MacaddrloMAC Address High Bytes Register Macaddrhi Macindex MAC Index Register MacindexMAC Index Register Macindex Field Descriptions TX nHDP Receive Channel 0-7 Completion Pointer Register RXnCP Transmit Channel 0-7 Completion Pointer Register TXnCPMulticast Receive Frames Register Rxmcastframes Network Statistics RegistersGood Receive Frames Register Rxgoodframes Broadcast Receive Frames Register RxbcastframesReceive Oversized Frames Register Rxoversized Receive CRC Errors Register RxcrcerrorsReceive Alignment/Code Errors Register Rxaligncodeerrors Pause Receive Frames Register RxpauseframesFiltered Receive Frames Register Rxfiltered Receive Jabber Frames Register RxjabberReceive Undersized Frames Register Rxundersized Receive Frame Fragments Register RxfragmentsGood Transmit Frames Register Txgoodframes Receive QOS Filtered Frames Register RxqosfilteredReceive Octet Frames Register Rxoctets Deferred Transmit Frames Register Txdeferred Broadcast Transmit Frames Register TxbcastframesMulticast Transmit Frames Register Txmcastframes Pause Transmit Frames Register TxpauseframesTransmit Late Collision Frames Register Txlatecoll Transmit Underrun Error Register TxunderrunTransmit Single Collision Frames Register Txsinglecoll Transmit Multiple Collision Frames Register TxmulticollTransmit and Receive 64 Octet Frames Register FRAME64 Transmit Carrier Sense Errors Register TxcarriersenseTransmit Octet Frames Register Txoctets Network Octet Frames Register Netoctets Receive DMA Overruns Register Rxdmaoverruns Appendix a Glossary Term Definition Table A-1. Physical Layer DefinitionsReference Additions/Modifications/Deletions Table B-1. Document Revision HistoryDSP Products Applications
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