Texas Instruments TMS320DM643X DMP manual End of Packet EOP Flag, Ownership Owner Flag

Page 22

www.ti.com

Peripheral Architecture

2.5.4.7End of Packet (EOP) Flag

When set, this flag indicates that the descriptor points to a packet buffer that is last for a given packet. In the case of a single fragment packet, both the start of packet (SOP) and EOP flags are set. Otherwise, the descriptor pointing to the last packet buffer for the packet sets the EOP flag. This bit is set by the software application and is not altered by the EMAC.

2.5.4.8Ownership (OWNER) Flag

When set, this flag indicates that all the descriptors for the given packet (from SOP to EOP) are currently owned by the EMAC. This flag is set by the software application on the SOP packet descriptor before adding the descriptor to the transmit descriptor queue. For a single fragment packet, the SOP, EOP, and OWNER flags are all set. The OWNER flag is cleared by the EMAC once it is finished with all the descriptors for the given packet. Note that this flag is valid on SOP descriptors only.

2.5.4.9End of Queue (EOQ) Flag

When set, this flag indicates that the descriptor in question was the last descriptor in the transmit queue for a given transmit channel, and that the transmitter has halted. This flag is initially cleared by the software application prior to adding the descriptor to the transmit queue. This bit is set by the EMAC when the EMAC identifies that a descriptor is the last for a given packet (the EOP flag is set), and there are no more descriptors in the transmit list (next descriptor pointer is NULL).

The software application can use this bit to detect when the EMAC transmitter for the corresponding channel has halted. This is useful when the application appends additional packet descriptors to a transmit queue list that is already owned by the EMAC. Note that this flag is valid on EOP descriptors only.

2.5.4.10Teardown Complete (TDOWNCMPLT) Flag

This flag is used when a transmit queue is being torn down, or aborted, instead of allowing it to be transmitted. This would happen under device driver reset or shutdown conditions. The EMAC sets this bit in the SOP descriptor of each packet as it is aborted from transmission.

Note that this flag is valid on SOP descriptors only. Also note that only the first packet in an unsent list has the TDOWNCMPLT flag set. Subsequent descriptors are not even processed by the EMAC.

2.5.4.11Pass CRC (PASSCRC) Flag

This flag is set by the software application in the SOP packet descriptor before it adds the descriptor to the transmit queue. Setting this bit indicates to the EMAC that the 4 byte Ethernet CRC is already present in the packet data, and that the EMAC should not generate its own version of the CRC.

When the CRC flag is cleared, the EMAC generates and appends the 4-byte CRC. The buffer length and packet length fields do not include the CRC bytes. When the CRC flag is set, the 4-byte CRC is supplied by the software application and is already appended to the end of the packet data. The buffer length and packet length fields include the CRC bytes, as they are part of the valid packet data. Note that this flag is valid on SOP descriptors only.

22 Ethernet Media Access Controller (EMAC)/SPRU941A –April 2007

Management Data Input/Output (MDIO)

Submit Documentation Feedback

 

Page 21 Page 23
Image 22
Page 21 Page 23
Contents Users Guide Submit Documentation Feedback Contents MAC Hash Address Register 1 MACHASH1 Appendix a Appendix BList of Figures Transmit Pacing Algorithm Test Register Tpacetest List of Tables Fifo Control Register Fifocontrol Field Descriptions Read This First Features Purpose of the PeripheralFunctional Block Diagram Emac and Mdio Block DiagramClock Control Signal DescriptionsIndustry Standards Compliance Statement Memory MapEmac and Mdio Signals Signal Type DescriptionEthernet Frame Description Ethernet Protocol OverviewEthernet Frame Format Field Bytes DescriptionProgramming Interface Ethernet’s Multiple Access ProtocolPacket Buffer Descriptors Basic Descriptor Description Typical Descriptor Linked ListTransmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Transmit Buffer Descriptor Format Example 1. Transmit Buffer Descriptor in C Structure FormatBuffer Offset Next Descriptor PointerBuffer Pointer Buffer LengthEnd of Queue EOQ Flag End of Packet EOP FlagOwnership Owner Flag Teardown Complete Tdowncmplt FlagReceive Buffer Descriptor Format Receive Buffer Descriptor FormatExample 2. Receive Buffer Descriptor in C Structure Format #define EmacdscflagjabberBuffer Length CRC Error Crcerror Flag Code Error Codeerror FlagAlignment Error Alignerror Flag Jabber FlagInternal Memory Emac Control ModuleNo Match Nomatch Flag Bus ArbiterInterrupt Control Mdio ModuleMdio Module Components Global PHY Detection and Link State Monitoring PHY Register User AccessMdio Clock Generator Active PHY MonitoringMdio Module Operational Overview Writing Data To a PHY Register Initializing the Mdio ModuleReading Data From a PHY Register Example of Mdio Register Access Code Example 3. Mdio Register Access MacrosReceive DMA Engine Emac ModuleEmac Module Components Receive FifoTransmit Fifo Clock and Reset LogicTransmit DMA Engine MAC TransmitterReceive Control Media Independent Interface MIIData Reception Receive Inter-Frame IntervalCollision-Based Receive Buffer Flow Control Ieee 802.3x-Based Receive Buffer Flow ControlAdaptive Performance Optimization APO Transmit ControlCRC Insertion Interpacket-Gap IPG EnforcementTransmit Flow Control Speed, Duplex, and Pause Frame SupportReceive Channel Enabling Receive DMA Host ConfigurationPacket Receive Operation Receive Address MatchingHost Free Buffer Tracking Hardware Receive QOS SupportReceive Channel Teardown Promiscuous Receive Mode Receive Frame ClassificationReceive Frame Treatment Summary Receive Frame TreatmentMiddle of Frame Overrun Treatment Receive OverrunMiddle of Frame Overrun Treatment Receive and Transmit Latency Transmit DMA Host ConfigurationPacket Transmit Operation Transmit Channel TeardownSoftware Reset Considerations Reset ConsiderationsTransfer Node Priority Enabling the EMAC/MDIO Peripheral Hardware Reset ConsiderationsInitialization Emac Control Module InitializationMdio Module Initialization Example 4. Emac Control Module Initialization CodeExample 5. Mdio Module Initialization Code Emac Module Initialization Transmit Packet Completion Interrupts Interrupt SupportEmac Module Interrupt Events and Requests Receive Packet Completion InterruptsHost Error Interrupt Statistics InterruptLink Change Interrupt User Access Completion InterruptMdio Module Interrupt Events and Requests Proper Interrupt ProcessingEmulation Considerations Power ManagementEmulation Control Acronym Register Description Emac Control Module Interrupt Control Register EwctlEmac Control Module Registers Bit FieldEmac Control Module Interrupt Timer Count Register Ewinttcnt Management Data Input/Output Mdio Registers Mdio Version Register VersionMdio Version Register Version Field Descriptions Mdio Control Register Control Mdio Control Register Control Field DescriptionsPHY Acknowledge Status Register Alive Field Descriptions PHY Acknowledge Status Register AlivePHY Link Status Register Link PHY Link Status Register Link Field DescriptionsNo Mdio link change event Will clear the event and writing a 0 has no effect No Mdio user command complete event USERINTMASKED0 and USERINTMASKED1 correspond to USERACCESS0 WS-0 Userintmaskclear Mdio User Access Register 0 USERACCESS0 Mdio User Access Register 0 USERACCESS0 Field DescriptionsPhyadrmon Mdio User PHY Select Register 0 USERPHYSEL0Linksel Linkintenb Bit Field Value DescriptionMdio User Access Register 1 USERACCESS1 Mdio User Access Register 1 USERACCESS1 Field DescriptionsMdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1Ethernet Media Access Controller Emac Registers Ethernet Media Access Controller Emac Registers Offset Acronym Register DescriptionOffset Acronym Register Description Network Statistics RegistersTransmit Control Register Txcontrol Transmit Identification and Version Register TxidverTransmit Control Register Txcontrol Field Descriptions Transmit Teardown Register Txteardown Field Descriptions Transmit Teardown Register TxteardownTxtdnch Receive Control Register Rxcontrol Receive Identification and Version Register RxidverReceive Control Register Rxcontrol Field Descriptions Receive Teardown Register Rxteardown Field Descriptions Receive Teardown Register RxteardownRxtdnch Transmit Interrupt Status Unmasked Register Txintstatraw TX7PENDTransmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register TxintstatmaskedTransmit Interrupt Mask Set Register Txintmaskset TX7MASKTransmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register TxintmaskclearUserint Linkint MAC Input Vector Register MacinvectorMAC Input Vector Register Macinvector Field Descriptions Hostpend Statpend Rxpend TxpendReceive Interrupt Status Unmasked Register Rxintstatraw RX7PENDReceive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register RxintstatmaskedReceive Interrupt Mask Set Register Rxintmaskset RX7MASKReceive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register RxintmaskclearMAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Status Unmasked Register MacintstatrawHostpend Statpend Hostmask Statmask MAC Interrupt Mask Set Register MacintmasksetMAC Interrupt Mask Clear Register Macintmaskclear HostmaskRxcsfen Rxcefen Rxcafen Rxpasscrc Rxqosen RxnochainRxcmfen RxpromchFrames containing errors are filtered Receive multicast channel select Receive Unicast Enable Set Register Rxunicastset RXCH7ENReceive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register RxunicastclearReceive Buffer Offset Register Rxbufferoffset Receive Maximum Length Register RxmaxlenReceive Maximum Length Register Rxmaxlen Field Descriptions Rxfilterthresh Reserved RX nFLOWTHRESH FFhReceive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol MAC Control Register Maccontrol Field DescriptionsSent. Full-duplex mode no outgoing pause frames are sent LoopbackMAC Status Register Macstatus MAC Status Register Macstatus Field DescriptionsMAC Status Register Macstatus Field Descriptions Bit Field Value DescriptionEmulation Control Register Emcontrol Field Descriptions Emulation Control Register EmcontrolFifo Control Register Fifocontrol Fifo Control Register Fifocontrol Field DescriptionsMAC Configuration Register Macconfig Field Descriptions MAC Configuration Register MacconfigSoft Reset Register Softreset Soft Reset Register Softreset Field DescriptionsMAC Source Address Low Bytes Register Macsrcaddrlo MAC Source Address High Bytes Register MacsrcaddrhiMAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 1 MACHASH1MAC Hash Address Register 2 MACHASH2 MAC Hash Address Register 2 MACHASH2 Field DescriptionsTransmit Pacing Algorithm Test Register Tpacetest Back Off Test Register BofftestBack Off Test Register Bofftest Field Descriptions Receive Pause Timer Register Rxpause Field Descriptions Receive Pause Timer Register RxpauseTransmit Pause Timer Register Txpause Transmit Pause Timer Register Txpause Field DescriptionsMAC Address High Bytes Register Macaddrhi MAC Address Low Bytes Register MacaddrloMAC Address Low Bytes Register Macaddrlo Field Descriptions MAC Index Register Macindex Field Descriptions MAC Index Register MacindexMacindex TX nHDP Transmit Channel 0-7 Completion Pointer Register TXnCP Receive Channel 0-7 Completion Pointer Register RXnCPBroadcast Receive Frames Register Rxbcastframes Network Statistics RegistersGood Receive Frames Register Rxgoodframes Multicast Receive Frames Register RxmcastframesPause Receive Frames Register Rxpauseframes Receive CRC Errors Register RxcrcerrorsReceive Alignment/Code Errors Register Rxaligncodeerrors Receive Oversized Frames Register RxoversizedReceive Frame Fragments Register Rxfragments Receive Jabber Frames Register RxjabberReceive Undersized Frames Register Rxundersized Filtered Receive Frames Register RxfilteredReceive Octet Frames Register Rxoctets Receive QOS Filtered Frames Register RxqosfilteredGood Transmit Frames Register Txgoodframes Pause Transmit Frames Register Txpauseframes Broadcast Transmit Frames Register TxbcastframesMulticast Transmit Frames Register Txmcastframes Deferred Transmit Frames Register TxdeferredTransmit Multiple Collision Frames Register Txmulticoll Transmit Underrun Error Register TxunderrunTransmit Single Collision Frames Register Txsinglecoll Transmit Late Collision Frames Register TxlatecollTransmit Octet Frames Register Txoctets Transmit Carrier Sense Errors Register TxcarriersenseTransmit and Receive 64 Octet Frames Register FRAME64 Network Octet Frames Register Netoctets Receive DMA Overruns Register Rxdmaoverruns Appendix a Glossary Table A-1. Physical Layer Definitions Term DefinitionTable B-1. Document Revision History Reference Additions/Modifications/DeletionsProducts Applications DSP
Related manuals
Manual 38 pages 8.14 Kb
Top Page Image Contents