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Figure 9. MDIO Module Block Diagram | ||
Peripheral | MDIO |
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clock |
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clock |
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| generator | MDIO |
USERINT |
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| interface | |
EMAC |
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control |
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module |
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LINKINT | PHY | PHY |
| monitoring | polling |
| Control |
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Configuration bus | registers |
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| and logic |
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Peripheral Architecture
MDCLK
MDIO
2.7.1.1MDIO Clock Generator
The MDIO clock generator controls the MDIO clock based on a
2.7.1.2Global PHY Detection and Link State Monitoring
The MDIO module continuously polls all 32 MDIO addresses in order to enumerate the PHY devices in the system. The module tracks whether or not a PHY on a particular address has responded, and whether or not the PHY currently has a link. Using this information allows the software application to quickly determine which MDIO address the PHY is using.
2.7.1.3Active PHY Monitoring
Once a PHY candidate has been selected for use, the MDIO module transparently monitors its link state by reading the MDIO PHY link status register (LINK). Link change events are stored on the MDIO device and can optionally interrupt the CPU. This allows the system to poll the link status of the PHY device without continuously performing costly MDIO accesses.
2.7.1.4PHY Register User Access
When the CPU must access MDIO for configuration and negotiation, the PHY access module performs the actual MDIO read or write operation independent of the CPU. This allows the CPU to poll for completion or receive an interrupt when the read or write operation has been performed. The user access registers USERACCESSn allows the software to submit the access requests for the PHY connected to the device.
SPRU941A
Submit Documentation Feedback | Management Data Input/Output (MDIO) |
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