Texas Instruments TMS320DM643X DMP manual Emac and Mdio Signals, Signal Type Description

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Peripheral Architecture

Figure 2. Typical Ethernet Configuration

System

core

EMAC

MDIO

MTCLK

MTXD(3−0)

MTXEN

MCOL

MCRS

MRCLK

MRXD(3−0)

MRXDV

MRXER

MDCLK

MDIO

Physical layer device (PHY)

2.5 MHz

or

25 MHz

Transformer

RJ−45

 

 

Table 1. EMAC and MDIO Signals

Signal

Type

Description

MTCLK

I

Transmit clock (MTCLK). The transmit clock is a continuous clock that provides the timing reference

 

 

for transmit operations. The MTXD and MTXEN signals are tied to this clock. The clock is generated

 

 

by the PHY and is 2.5 MHz at 10 Mbps operation and 25 MHz at 100 Mbps operation.

MTXD[3-0]

O

Transmit data (MTXD). The transmit data pins are a collection of 4 data signals comprising 4 bits of

 

 

data. MTDX0 is the least-significant bit (LSB). The signals are synchronized by MTCLK and valid

 

 

only when MTXEN is asserted.

MTXEN

O

Transmit enable (MTXEN). The transmit enable signal indicates that the MTXD pins are generating

 

 

nibble data for use by the PHY. It is driven synchronously to MTCLK.

MCOL

I

Collision detected (MCOL). The MCOL pin is asserted by the PHY when it detects a collision on the

 

 

network. It remains asserted while the collision condition persists. This signal is not necessarily

 

 

synchronous to MTCLK nor MRCLK. This pin is used in half-duplex operation only.

MCRS

I

Carrier sense (MCRS). The MCRS pin is asserted by the PHY when the network is not idle in either

 

 

transmit or receive. The pin is deasserted when both transmit and receive are idle. This signal is not

 

 

necessarily synchronous to MTCLK nor MRCLK. This pin is used in half-duplex operation only.

MRCLK

I

Receive clock (MRCLK). The receive clock is a continuous clock that provides the timing reference

 

 

for receive operations. The MRXD, MRXDV, and MRXER signals are tied to this clock. The clock is

 

 

generated by the PHY and is 2.5 MHz at 10 Mbps operation and 25 MHz at 100 Mbps operation.

MRXD[3-0]

I

Receive data (MRXD). The receive data pins are a collection of 4 data signals comprising 4 bits of

 

 

data. MRDX0 is the least-significant bit (LSB). The signals are synchronized by MRCLK and valid

 

 

only when MRXDV is asserted.

MRXDV

I

Receive data valid (MRXDV). The receive data valid signal indicates that the MRXD pins are

 

 

generating nibble data for use by the EMAC. It is driven synchronously to MRCLK.

MRXER

I

Receive error (MRXER). The receive error signal is asserted for one or more MRCLK periods to

 

 

indicate that an error was detected in the received frame. This is meaningful only during data

 

 

reception when MRXDV is active.

MDCLK

O

Management data clock (MDCLK). The MDIO data clock is sourced by the MDIO module on the

 

 

system. It is used to synchronize MDIO data access operations done on the MDIO pin. The

 

 

frequency of this clock is controlled by the CLKDIV bits in the MDIO control register (CONTROL).

MDIO

I/O

Management data input output (MDIO). The MDIO pin drives PHY management data into and out of

 

 

the PHY by way of an access frame consisting of start of frame, read/write indication, PHY address,

 

 

register address, and data bit cycles. The MDIO pin acts as an output for all but the data bit cycles

 

 

at which time it is an input for read operations.

14 Ethernet Media Access Controller (EMAC)/SPRU941A –April 2007

Management Data Input/Output (MDIO)

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Contents Users Guide Submit Documentation Feedback Contents MAC Hash Address Register 1 MACHASH1 Appendix a Appendix BList of Figures Transmit Pacing Algorithm Test Register Tpacetest List of Tables Fifo Control Register Fifocontrol Field Descriptions Read This First Features Purpose of the PeripheralFunctional Block Diagram Emac and Mdio Block DiagramClock Control Signal DescriptionsIndustry Standards Compliance Statement Memory MapEmac and Mdio Signals Signal Type DescriptionEthernet Frame Description Ethernet Protocol OverviewEthernet Frame Format Field Bytes DescriptionPacket Buffer Descriptors Ethernet’s Multiple Access ProtocolProgramming Interface Basic Descriptor Description Typical Descriptor Linked ListTransmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Transmit Buffer Descriptor Format Example 1. Transmit Buffer Descriptor in C Structure FormatBuffer Offset Next Descriptor PointerBuffer Pointer Buffer LengthEnd of Queue EOQ Flag End of Packet EOP FlagOwnership Owner Flag Teardown Complete Tdowncmplt FlagReceive Buffer Descriptor Format Receive Buffer Descriptor FormatExample 2. Receive Buffer Descriptor in C Structure Format #define EmacdscflagjabberBuffer Length CRC Error Crcerror Flag Code Error Codeerror FlagAlignment Error Alignerror Flag Jabber FlagInternal Memory Emac Control ModuleNo Match Nomatch Flag Bus ArbiterMdio Module Components Mdio ModuleInterrupt Control Global PHY Detection and Link State Monitoring PHY Register User AccessMdio Clock Generator Active PHY MonitoringMdio Module Operational Overview Reading Data From a PHY Register Initializing the Mdio ModuleWriting Data To a PHY Register Example of Mdio Register Access Code Example 3. Mdio Register Access MacrosReceive DMA Engine Emac ModuleEmac Module Components Receive FifoTransmit Fifo Clock and Reset LogicTransmit DMA Engine MAC TransmitterReceive Control Media Independent Interface MIIData Reception Receive Inter-Frame IntervalCollision-Based Receive Buffer Flow Control Ieee 802.3x-Based Receive Buffer Flow ControlAdaptive Performance Optimization APO Transmit ControlCRC Insertion Interpacket-Gap IPG EnforcementTransmit Flow Control Speed, Duplex, and Pause Frame SupportReceive Channel Enabling Receive DMA Host ConfigurationPacket Receive Operation Receive Address MatchingReceive Channel Teardown Hardware Receive QOS SupportHost Free Buffer Tracking Promiscuous Receive Mode Receive Frame ClassificationReceive Frame Treatment Summary Receive Frame TreatmentMiddle of Frame Overrun Treatment Receive OverrunMiddle of Frame Overrun Treatment Receive and Transmit Latency Transmit DMA Host ConfigurationPacket Transmit Operation Transmit Channel TeardownTransfer Node Priority Reset ConsiderationsSoftware Reset Considerations Enabling the EMAC/MDIO Peripheral Hardware Reset ConsiderationsInitialization Emac Control Module InitializationExample 5. Mdio Module Initialization Code Example 4. Emac Control Module Initialization CodeMdio Module Initialization Emac Module Initialization Transmit Packet Completion Interrupts Interrupt SupportEmac Module Interrupt Events and Requests Receive Packet Completion InterruptsHost Error Interrupt Statistics InterruptLink Change Interrupt User Access Completion InterruptMdio Module Interrupt Events and Requests Proper Interrupt ProcessingEmulation Control Power ManagementEmulation Considerations Acronym Register Description Emac Control Module Interrupt Control Register EwctlEmac Control Module Registers Bit FieldEmac Control Module Interrupt Timer Count Register Ewinttcnt Mdio Version Register Version Field Descriptions Mdio Version Register VersionManagement Data Input/Output Mdio Registers Mdio Control Register Control Mdio Control Register Control Field DescriptionsPHY Acknowledge Status Register Alive Field Descriptions PHY Acknowledge Status Register AlivePHY Link Status Register Link PHY Link Status Register Link Field DescriptionsNo Mdio link change event Will clear the event and writing a 0 has no effect No Mdio user command complete event USERINTMASKED0 and USERINTMASKED1 correspond to USERACCESS0 WS-0 Userintmaskclear Mdio User Access Register 0 USERACCESS0 Mdio User Access Register 0 USERACCESS0 Field DescriptionsPhyadrmon Mdio User PHY Select Register 0 USERPHYSEL0Linksel Linkintenb Bit Field Value DescriptionMdio User Access Register 1 USERACCESS1 Mdio User Access Register 1 USERACCESS1 Field DescriptionsMdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1Ethernet Media Access Controller Emac Registers Ethernet Media Access Controller Emac Registers Offset Acronym Register DescriptionOffset Acronym Register Description Network Statistics RegistersTransmit Control Register Txcontrol Field Descriptions Transmit Identification and Version Register TxidverTransmit Control Register Txcontrol Txtdnch Transmit Teardown Register TxteardownTransmit Teardown Register Txteardown Field Descriptions Receive Control Register Rxcontrol Field Descriptions Receive Identification and Version Register RxidverReceive Control Register Rxcontrol Rxtdnch Receive Teardown Register RxteardownReceive Teardown Register Rxteardown Field Descriptions Transmit Interrupt Status Unmasked Register Txintstatraw TX7PENDTransmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register TxintstatmaskedTransmit Interrupt Mask Set Register Txintmaskset TX7MASKTransmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register TxintmaskclearUserint Linkint MAC Input Vector Register MacinvectorMAC Input Vector Register Macinvector Field Descriptions Hostpend Statpend Rxpend TxpendReceive Interrupt Status Unmasked Register Rxintstatraw RX7PENDReceive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register RxintstatmaskedReceive Interrupt Mask Set Register Rxintmaskset RX7MASKReceive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register RxintmaskclearHostpend Statpend MAC Interrupt Status Unmasked Register MacintstatrawMAC Interrupt Status Masked Register Macintstatmasked Hostmask Statmask MAC Interrupt Mask Set Register MacintmasksetMAC Interrupt Mask Clear Register Macintmaskclear HostmaskRxcsfen Rxcefen Rxcafen Rxpasscrc Rxqosen RxnochainRxcmfen RxpromchFrames containing errors are filtered Receive multicast channel select Receive Unicast Enable Set Register Rxunicastset RXCH7ENReceive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register RxunicastclearReceive Maximum Length Register Rxmaxlen Field Descriptions Receive Maximum Length Register RxmaxlenReceive Buffer Offset Register Rxbufferoffset Rxfilterthresh Reserved RX nFLOWTHRESH FFhReceive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol MAC Control Register Maccontrol Field DescriptionsSent. Full-duplex mode no outgoing pause frames are sent LoopbackMAC Status Register Macstatus MAC Status Register Macstatus Field DescriptionsMAC Status Register Macstatus Field Descriptions Bit Field Value DescriptionEmulation Control Register Emcontrol Field Descriptions Emulation Control Register EmcontrolFifo Control Register Fifocontrol Fifo Control Register Fifocontrol Field DescriptionsMAC Configuration Register Macconfig Field Descriptions MAC Configuration Register MacconfigSoft Reset Register Softreset Soft Reset Register Softreset Field DescriptionsMAC Source Address Low Bytes Register Macsrcaddrlo MAC Source Address High Bytes Register MacsrcaddrhiMAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 1 MACHASH1MAC Hash Address Register 2 MACHASH2 MAC Hash Address Register 2 MACHASH2 Field DescriptionsBack Off Test Register Bofftest Field Descriptions Back Off Test Register BofftestTransmit Pacing Algorithm Test Register Tpacetest Receive Pause Timer Register Rxpause Field Descriptions Receive Pause Timer Register RxpauseTransmit Pause Timer Register Txpause Transmit Pause Timer Register Txpause Field DescriptionsMAC Address Low Bytes Register Macaddrlo Field Descriptions MAC Address Low Bytes Register MacaddrloMAC Address High Bytes Register Macaddrhi Macindex MAC Index Register MacindexMAC Index Register Macindex Field Descriptions TX nHDP Transmit Channel 0-7 Completion Pointer Register TXnCP Receive Channel 0-7 Completion Pointer Register RXnCPBroadcast Receive Frames Register Rxbcastframes Network Statistics RegistersGood Receive Frames Register Rxgoodframes Multicast Receive Frames Register RxmcastframesPause Receive Frames Register Rxpauseframes Receive CRC Errors Register RxcrcerrorsReceive Alignment/Code Errors Register Rxaligncodeerrors Receive Oversized Frames Register RxoversizedReceive Frame Fragments Register Rxfragments Receive Jabber Frames Register RxjabberReceive Undersized Frames Register Rxundersized Filtered Receive Frames Register RxfilteredGood Transmit Frames Register Txgoodframes Receive QOS Filtered Frames Register RxqosfilteredReceive Octet Frames Register Rxoctets Pause Transmit Frames Register Txpauseframes Broadcast Transmit Frames Register TxbcastframesMulticast Transmit Frames Register Txmcastframes Deferred Transmit Frames Register TxdeferredTransmit Multiple Collision Frames Register Txmulticoll Transmit Underrun Error Register TxunderrunTransmit Single Collision Frames Register Txsinglecoll Transmit Late Collision Frames Register TxlatecollTransmit and Receive 64 Octet Frames Register FRAME64 Transmit Carrier Sense Errors Register TxcarriersenseTransmit Octet Frames Register Txoctets Network Octet Frames Register Netoctets Receive DMA Overruns Register Rxdmaoverruns Appendix a Glossary Table A-1. Physical Layer Definitions Term DefinitionTable B-1. Document Revision History Reference Additions/Modifications/DeletionsProducts Applications DSP
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