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Ethernet Media Access Controller (EMAC) Registers
5Ethernet Media Access Controller (EMAC) Registers
Table 25 lists the
Table 25. Ethernet Media Access Controller (EMAC) Registers
Offset | Acronym | Register Description | Section |
0h | TXIDVER | Transmit Identification and Version Register | Section 5.1 |
4h | TXCONTROL | Transmit Control Register | Section 5.2 |
8h | TXTEARDOWN | Transmit Teardown Register | Section 5.3 |
10h | RXIDVER | Receive Identification and Version Register | Section 5.4 |
14h | RXCONTROL | Receive Control Register | Section 5.5 |
18h | RXTEARDOWN | Receive Teardown Register | Section 5.6 |
80h | TXINTSTATRAW | Transmit Interrupt Status (Unmasked) Register | Section 5.7 |
84h | TXINTSTATMASKED | Transmit Interrupt Status (Masked) Register | Section 5.8 |
88h | TXINTMASKSET | Transmit Interrupt Mask Set Register | Section 5.9 |
8Ch | TXINTMASKCLEAR | Transmit Interrupt Clear Register | Section 5.10 |
90h | MACINVECTOR | MAC Input Vector Register | Section 5.11 |
A0h | RXINTSTATRAW | Receive Interrupt Status (Unmasked) Register | Section 5.12 |
A4h | RXINTSTATMASKED | Receive Interrupt Status (Masked) Register | Section 5.13 |
A8h | RXINTMASKSET | Receive Interrupt Mask Set Register | Section 5.14 |
ACh | RXINTMASKCLEAR | Receive Interrupt Mask Clear Register | Section 5.15 |
B0h | MACINTSTATRAW | MAC Interrupt Status (Unmasked) Register | Section 5.16 |
B4h | MACINTSTATMASKED | MAC Interrupt Status (Masked) Register | Section 5.17 |
B8h | MACINTMASKSET | MAC Interrupt Mask Set Register | Section 5.18 |
BCh | MACINTMASKCLEAR | MAC Interrupt Mask Clear Register | Section 5.19 |
100h | RXMBPENABLE | Receive Multicast/Broadcast/Promiscuous Channel Enable Register | Section 5.20 |
104h | RXUNICASTSET | Receive Unicast Enable Set Register | Section 5.21 |
108h | RXUNICASTCLEAR | Receive Unicast Clear Register | Section 5.22 |
10Ch | RXMAXLEN | Receive Maximum Length Register | Section 5.23 |
110h | RXBUFFEROFFSET | Receive Buffer Offset Register | Section 5.24 |
114h | RXFILTERLOWTHRESH | Receive Filter Low Priority Frame Threshold Register | Section 5.25 |
120h | RX0FLOWTHRESH | Receive Channel 0 Flow Control Threshold Register | Section 5.26 |
124h | RX1FLOWTHRESH | Receive Channel 1 Flow Control Threshold Register | Section 5.26 |
128h | RX2FLOWTHRESH | Receive Channel 2 Flow Control Threshold Register | Section 5.26 |
12Ch | RX3FLOWTHRESH | Receive Channel 3 Flow Control Threshold Register | Section 5.26 |
130h | RX4FLOWTHRESH | Receive Channel 4 Flow Control Threshold Register | Section 5.26 |
134h | RX5FLOWTHRESH | Receive Channel 5 Flow Control Threshold Register | Section 5.26 |
138h | RX6FLOWTHRESH | Receive Channel 6 Flow Control Threshold Register | Section 5.26 |
13Ch | RX7FLOWTHRESH | Receive Channel 7 Flow Control Threshold Register | Section 5.26 |
140h | RX0FREEBUFFER | Receive Channel 0 Free Buffer Count Register | Section 5.27 |
144h | RX1FREEBUFFER | Receive Channel 1 Free Buffer Count Register | Section 5.27 |
148h | RX2FREEBUFFER | Receive Channel 2 Free Buffer Count Register | Section 5.27 |
14Ch | RX3FREEBUFFER | Receive Channel 3 Free Buffer Count Register | Section 5.27 |
150h | RX4FREEBUFFER | Receive Channel 4 Free Buffer Count Register | Section 5.27 |
154h | RX5FREEBUFFER | Receive Channel 5 Free Buffer Count Register | Section 5.27 |
158h | RX6FREEBUFFER | Receive Channel 6 Free Buffer Count Register | Section 5.27 |
15Ch | RX7FREEBUFFER | Receive Channel 7 Free Buffer Count Register | Section 5.27 |
160h | MACCONTROL | MAC Control Register | Section 5.28 |
164h | MACSTATUS | MAC Status Register | Section 5.29 |
68 Ethernet Media Access Controller (EMAC)/SPRU941A
Management Data Input/Output (MDIO) | Submit Documentation Feedback |
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