Texas Instruments TMS320DM643X DMP manual Offset Acronym Register Description

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Ethernet Media Access Controller (EMAC) Registers

Table 25. Ethernet Media Access Controller (EMAC) Registers (continued)

Offset

Acronym

Register Description

Section

67Ch

RX7CP

Receive Channel 7 Completion Pointer Register

Section 5.48

 

 

Network Statistics Registers

 

200h

RXGOODFRAMES

Good Receive Frames Register

Section 5.49.1

204h

RXBCASTFRAMES

Broadcast Receive Frames Register

Section 5.49.2

208h

RXMCASTFRAMES

Multicast Receive Frames Register

Section 5.49.3

20Ch

RXPAUSEFRAMES

Pause Receive Frames Register

Section 5.49.4

210h

RXCRCERRORS

Receive CRC Errors Register

Section 5.49.5

214h

RXALIGNCODEERRORS

Receive Alignment/Code Errors Register

Section 5.49.6

218h

RXOVERSIZED

Receive Oversized Frames Register

Section 5.49.7

21Ch

RXJABBER

Receive Jabber Frames Register

Section 5.49.8

220h

RXUNDERSIZED

Receive Undersized Frames Register

Section 5.49.9

224h

RXFRAGMENTS

Receive Frame Fragments Register

Section 5.49.10

228h

RXFILTERED

Filtered Receive Frames Register

Section 5.49.11

22Ch

RXQOSFILTERED

Receive QOS Filtered Frames Register

Section 5.49.12

230h

RXOCTETS

Receive Octet Frames Register

Section 5.49.13

234h

TXGOODFRAMES

Good Transmit Frames Register

Section 5.49.14

238h

TXBCASTFRAMES

Broadcast Transmit Frames Register

Section 5.49.15

23Ch

TXMCASTFRAMES

Multicast Transmit Frames Register

Section 5.49.16

240h

TXPAUSEFRAMES

Pause Transmit Frames Register

Section 5.49.17

244h

TXDEFERRED

Deferred Transmit Frames Register

Section 5.49.18

248h

TXCOLLISION

Transmit Collision Frames Register

Section 5.49.19

24Ch

TXSINGLECOLL

Transmit Single Collision Frames Register

Section 5.49.20

250h

TXMULTICOLL

Transmit Multiple Collision Frames Register

Section 5.49.21

254h

TXEXCESSIVECOLL

Transmit Excessive Collision Frames Register

Section 5.49.22

258h

TXLATECOLL

Transmit Late Collision Frames Register

Section 5.49.23

25Ch

TXUNDERRUN

Transmit Underrun Error Register

Section 5.49.24

260h

TXCARRIERSENSE

Transmit Carrier Sense Errors Register

Section 5.49.25

264h

TXOCTETS

Transmit Octet Frames Register

Section 5.49.26

268h

FRAME64

Transmit and Receive 64 Octet Frames Register

Section 5.49.27

26Ch

FRAME65T127

Transmit and Receive 65 to 127 Octet Frames Register

Section 5.49.28

270h

FRAME128T255

Transmit and Receive 128 to 255 Octet Frames Register

Section 5.49.29

274h

FRAME256T511

Transmit and Receive 256 to 511 Octet Frames Register

Section 5.49.30

278h

FRAME512T1023

Transmit and Receive 512 to 1023 Octet Frames Register

Section 5.49.31

27Ch

FRAME1024TUP

Transmit and Receive 1024 to RXMAXLEN Octet Frames Register

Section 5.49.32

280h

NETOCTETS

Network Octet Frames Register

Section 5.49.33

284h

RXSOFOVERRUNS

Receive FIFO or DMA Start of Frame Overruns Register

Section 5.49.34

288h

RXMOFOVERRUNS

Receive FIFO or DMA Middle of Frame Overruns Register

Section 5.49.35

28Ch

RXDMAOVERRUNS

Receive DMA Overruns Register

Section 5.49.36

70 Ethernet Media Access Controller (EMAC)/SPRU941A –April 2007

Management Data Input/Output (MDIO)

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Contents Users Guide Submit Documentation Feedback Contents MAC Hash Address Register 1 MACHASH1 Appendix a Appendix BList of Figures Transmit Pacing Algorithm Test Register Tpacetest List of Tables Fifo Control Register Fifocontrol Field Descriptions Read This First Features Purpose of the PeripheralFunctional Block Diagram Emac and Mdio Block DiagramClock Control Signal DescriptionsIndustry Standards Compliance Statement Memory MapEmac and Mdio Signals Signal Type DescriptionEthernet Frame Description Ethernet Protocol OverviewEthernet Frame Format Field Bytes DescriptionProgramming Interface Ethernet’s Multiple Access ProtocolPacket Buffer Descriptors Basic Descriptor Description Typical Descriptor Linked ListTransmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Transmit Buffer Descriptor Format Example 1. Transmit Buffer Descriptor in C Structure FormatBuffer Offset Next Descriptor PointerBuffer Pointer Buffer LengthEnd of Queue EOQ Flag End of Packet EOP FlagOwnership Owner Flag Teardown Complete Tdowncmplt FlagReceive Buffer Descriptor Format Receive Buffer Descriptor FormatExample 2. Receive Buffer Descriptor in C Structure Format #define EmacdscflagjabberBuffer Length CRC Error Crcerror Flag Code Error Codeerror FlagAlignment Error Alignerror Flag Jabber FlagInternal Memory Emac Control ModuleNo Match Nomatch Flag Bus ArbiterInterrupt Control Mdio ModuleMdio Module Components Global PHY Detection and Link State Monitoring PHY Register User AccessMdio Clock Generator Active PHY MonitoringMdio Module Operational Overview Writing Data To a PHY Register Initializing the Mdio ModuleReading Data From a PHY Register Example of Mdio Register Access Code Example 3. Mdio Register Access MacrosReceive DMA Engine Emac ModuleEmac Module Components Receive FifoTransmit Fifo Clock and Reset LogicTransmit DMA Engine MAC TransmitterReceive Control Media Independent Interface MIIData Reception Receive Inter-Frame IntervalCollision-Based Receive Buffer Flow Control Ieee 802.3x-Based Receive Buffer Flow ControlAdaptive Performance Optimization APO Transmit ControlCRC Insertion Interpacket-Gap IPG EnforcementTransmit Flow Control Speed, Duplex, and Pause Frame SupportReceive Channel Enabling Receive DMA Host ConfigurationPacket Receive Operation Receive Address MatchingHost Free Buffer Tracking Hardware Receive QOS SupportReceive Channel Teardown Promiscuous Receive Mode Receive Frame ClassificationReceive Frame Treatment Summary Receive Frame TreatmentMiddle of Frame Overrun Treatment Receive OverrunMiddle of Frame Overrun Treatment Receive and Transmit Latency Transmit DMA Host ConfigurationPacket Transmit Operation Transmit Channel TeardownSoftware Reset Considerations Reset ConsiderationsTransfer Node Priority Enabling the EMAC/MDIO Peripheral Hardware Reset ConsiderationsInitialization Emac Control Module InitializationMdio Module Initialization Example 4. Emac Control Module Initialization CodeExample 5. Mdio Module Initialization Code Emac Module Initialization Transmit Packet Completion Interrupts Interrupt SupportEmac Module Interrupt Events and Requests Receive Packet Completion InterruptsHost Error Interrupt Statistics InterruptLink Change Interrupt User Access Completion InterruptMdio Module Interrupt Events and Requests Proper Interrupt ProcessingEmulation Considerations Power ManagementEmulation Control Acronym Register Description Emac Control Module Interrupt Control Register EwctlEmac Control Module Registers Bit FieldEmac Control Module Interrupt Timer Count Register Ewinttcnt Management Data Input/Output Mdio Registers Mdio Version Register VersionMdio Version Register Version Field Descriptions Mdio Control Register Control Mdio Control Register Control Field DescriptionsPHY Acknowledge Status Register Alive Field Descriptions PHY Acknowledge Status Register AlivePHY Link Status Register Link PHY Link Status Register Link Field DescriptionsNo Mdio link change event Will clear the event and writing a 0 has no effect No Mdio user command complete event USERINTMASKED0 and USERINTMASKED1 correspond to USERACCESS0 WS-0 Userintmaskclear Mdio User Access Register 0 USERACCESS0 Mdio User Access Register 0 USERACCESS0 Field DescriptionsPhyadrmon Mdio User PHY Select Register 0 USERPHYSEL0Linksel Linkintenb Bit Field Value DescriptionMdio User Access Register 1 USERACCESS1 Mdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1Ethernet Media Access Controller Emac Registers Ethernet Media Access Controller Emac Registers Offset Acronym Register DescriptionOffset Acronym Register Description Network Statistics RegistersTransmit Control Register Txcontrol Transmit Identification and Version Register TxidverTransmit Control Register Txcontrol Field Descriptions Transmit Teardown Register Txteardown Field Descriptions Transmit Teardown Register TxteardownTxtdnch Receive Control Register Rxcontrol Receive Identification and Version Register RxidverReceive Control Register Rxcontrol Field Descriptions Receive Teardown Register Rxteardown Field Descriptions Receive Teardown Register RxteardownRxtdnch Transmit Interrupt Status Unmasked Register Txintstatraw TX7PENDTransmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register TxintstatmaskedTransmit Interrupt Mask Set Register Txintmaskset TX7MASKTransmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register TxintmaskclearUserint Linkint MAC Input Vector Register MacinvectorMAC Input Vector Register Macinvector Field Descriptions Hostpend Statpend Rxpend TxpendReceive Interrupt Status Unmasked Register Rxintstatraw RX7PENDReceive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register RxintstatmaskedReceive Interrupt Mask Set Register Rxintmaskset RX7MASKReceive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register RxintmaskclearMAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Status Unmasked Register MacintstatrawHostpend Statpend Hostmask Statmask MAC Interrupt Mask Set Register MacintmasksetMAC Interrupt Mask Clear Register Macintmaskclear HostmaskRxcsfen Rxcefen Rxcafen Rxpasscrc Rxqosen RxnochainRxcmfen RxpromchFrames containing errors are filtered Receive multicast channel select Receive Unicast Enable Set Register Rxunicastset RXCH7ENReceive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register RxunicastclearReceive Buffer Offset Register Rxbufferoffset Receive Maximum Length Register RxmaxlenReceive Maximum Length Register Rxmaxlen Field Descriptions Rxfilterthresh Reserved RX nFLOWTHRESH FFhReceive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol MAC Control Register Maccontrol Field DescriptionsSent. Full-duplex mode no outgoing pause frames are sent LoopbackMAC Status Register Macstatus MAC Status Register Macstatus Field DescriptionsMAC Status Register Macstatus Field Descriptions Bit Field Value DescriptionEmulation Control Register Emcontrol Field Descriptions Emulation Control Register EmcontrolFifo Control Register Fifocontrol Fifo Control Register Fifocontrol Field DescriptionsMAC Configuration Register Macconfig Field Descriptions MAC Configuration Register MacconfigSoft Reset Register Softreset Soft Reset Register Softreset Field DescriptionsMAC Source Address Low Bytes Register Macsrcaddrlo MAC Source Address High Bytes Register MacsrcaddrhiMAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 1 MACHASH1MAC Hash Address Register 2 MACHASH2 MAC Hash Address Register 2 MACHASH2 Field DescriptionsTransmit Pacing Algorithm Test Register Tpacetest Back Off Test Register BofftestBack Off Test Register Bofftest Field Descriptions Receive Pause Timer Register Rxpause Field Descriptions Receive Pause Timer Register RxpauseTransmit Pause Timer Register Txpause Transmit Pause Timer Register Txpause Field DescriptionsMAC Address High Bytes Register Macaddrhi MAC Address Low Bytes Register MacaddrloMAC Address Low Bytes Register Macaddrlo Field Descriptions MAC Index Register Macindex Field Descriptions MAC Index Register MacindexMacindex TX nHDP Transmit Channel 0-7 Completion Pointer Register TXnCP Receive Channel 0-7 Completion Pointer Register RXnCPBroadcast Receive Frames Register Rxbcastframes Network Statistics RegistersGood Receive Frames Register Rxgoodframes Multicast Receive Frames Register RxmcastframesPause Receive Frames Register Rxpauseframes Receive CRC Errors Register RxcrcerrorsReceive Alignment/Code Errors Register Rxaligncodeerrors Receive Oversized Frames Register RxoversizedReceive Frame Fragments Register Rxfragments Receive Jabber Frames Register RxjabberReceive Undersized Frames Register Rxundersized Filtered Receive Frames Register RxfilteredReceive Octet Frames Register Rxoctets Receive QOS Filtered Frames Register RxqosfilteredGood Transmit Frames Register Txgoodframes Pause Transmit Frames Register Txpauseframes Broadcast Transmit Frames Register TxbcastframesMulticast Transmit Frames Register Txmcastframes Deferred Transmit Frames Register TxdeferredTransmit Multiple Collision Frames Register Txmulticoll Transmit Underrun Error Register TxunderrunTransmit Single Collision Frames Register Txsinglecoll Transmit Late Collision Frames Register TxlatecollTransmit Octet Frames Register Txoctets Transmit Carrier Sense Errors Register TxcarriersenseTransmit and Receive 64 Octet Frames Register FRAME64 Network Octet Frames Register Netoctets Receive DMA Overruns Register Rxdmaoverruns Appendix a Glossary Table A-1. Physical Layer Definitions Term DefinitionTable B-1. Document Revision History Reference Additions/Modifications/DeletionsProducts Applications DSP
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