Texas Instruments TMS320DM643X DMP manual Transfer Node Priority, Reset Considerations

Page 45

www.ti.com

Peripheral Architecture

Latency to system’s internal and external RAM can be controlled through the use of the transfer node priority allocation register available at the device level. Latency to descriptor RAM is low because RAM is local to the EMAC, as it is part of the EMAC control module.

2.13 Transfer Node Priority

The DM643x device contains a chip-level register, master priority register (MSTPRI), that is used to set the priority of the transfer node used in issuing memory transfer requests to system memory.

Although the EMAC has internal FIFOs to help alleviate memory transfer arbitration problems, the average transfer rate of data read and written by the EMAC to internal or external processor memory must be at least that of the Ethernet wire rate. In addition, the internal FIFO system can not withstand a single memory latency event greater than the time it takes to fill or empty a TXCELLTHRESH number of internal 64 byte FIFO cells.

For 100 Mbps operation, these restrictions translate into the following rules:

∙The short-term average, each 64-byte memory read/write request from the EMAC must be serviced in no more than 5.12 μs.

∙Any single latency event in request servicing can be no longer than (5.12 × TXCELLTHRESH) μs.

Bits [0-2] of the second chip-level master priority register (MSTPRI1) are used to set the transfer node priority within the Switched Central Resource (SCR5) for the EMAC master peripheral.

A value of 000b has the highest priority, while 111b has the lowest priority. The default priority assigned to the EMAC is 100b. It is important to have a balance between all peripherals. In most cases, the default priorities will not need adjustment. For more information on the master peripherals priorities, see the device-specific data manual.

2.14 Reset Considerations

2.14.1Software Reset Considerations

Peripheral clock and reset control is done through the Power and Sleep Controller (PSC) module included with the device. For more on how the EMAC, MDIO, and EMAC control module are disabled or placed in reset at runtime from the registers located in the PSC module, see Section 2.17.

With the EMAC still in reset (PSC in the default state):

1.Program the PINMUX1 register to HOSTBK = 3h or 4h (MII).

2.Program the VDD3P3V_PWDN register to power up the IO pins for MII pins (see the device-specific data manual).

3.Program the PSC to enale the EMAC. For information on how to enable the EMAC peripheral from the PSC, see the TMS320DM643x DMP DSP Subsystem Reference Guide (SPRU978).

Within the peripheral itself, the EMAC component of the Ethernet MAC peripheral can be placed in a reset state by writing to the soft reset register (SOFTRESET). Writing a 1 to the SOFTRESET bit, causes the EMAC logic to be reset and the register values to be set to their default values. Software reset occurs when the receive and transmit DMA controllers are in an idle state to avoid locking up the configuration bus; it is the responsibility of the software to verify that there are no pending frames to be transferred. After writing a 1 to the SOFTRESET bit, it may be polled to determine if the reset has occurred. If a 1 is read, the reset has not yet occurred; if a 0 is read, then a reset has occurred.

After a software reset operation, all the EMAC registers need to be reinitialized for proper data transmission, including the FULLDUPLEX bit setting in the MAC control register (MACCONTROL).

Unlike the EMAC module, the MDIO and EMAC control modules cannot be placed in reset from a register inside their memory map.

SPRU941A –April 2007Ethernet Media Access Controller (EMAC)/ 45

Submit Documentation Feedback

Management Data Input/Output (MDIO)

 

Page 44 Page 46
Image 45
Page 44 Page 46
Contents Users Guide Submit Documentation Feedback Contents MAC Hash Address Register 1 MACHASH1 Appendix B Appendix aList of Figures Transmit Pacing Algorithm Test Register Tpacetest List of Tables Fifo Control Register Fifocontrol Field Descriptions Read This First Purpose of the Peripheral FeaturesEmac and Mdio Block Diagram Functional Block DiagramIndustry Standards Compliance Statement Signal DescriptionsClock Control Memory MapSignal Type Description Emac and Mdio SignalsEthernet Frame Format Ethernet Protocol OverviewEthernet Frame Description Field Bytes DescriptionEthernet’s Multiple Access Protocol Programming InterfacePacket Buffer Descriptors Typical Descriptor Linked List Basic Descriptor DescriptionTransmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Example 1. Transmit Buffer Descriptor in C Structure Format Transmit Buffer Descriptor FormatBuffer Pointer Next Descriptor PointerBuffer Offset Buffer LengthOwnership Owner Flag End of Packet EOP FlagEnd of Queue EOQ Flag Teardown Complete Tdowncmplt FlagReceive Buffer Descriptor Format Receive Buffer Descriptor Format#define Emacdscflagjabber Example 2. Receive Buffer Descriptor in C Structure FormatBuffer Length Alignment Error Alignerror Flag Code Error Codeerror FlagCRC Error Crcerror Flag Jabber FlagNo Match Nomatch Flag Emac Control ModuleInternal Memory Bus ArbiterMdio Module Interrupt ControlMdio Module Components Mdio Clock Generator PHY Register User AccessGlobal PHY Detection and Link State Monitoring Active PHY MonitoringMdio Module Operational Overview Initializing the Mdio Module Writing Data To a PHY RegisterReading Data From a PHY Register Example 3. Mdio Register Access Macros Example of Mdio Register Access CodeEmac Module Components Emac ModuleReceive DMA Engine Receive FifoTransmit DMA Engine Clock and Reset LogicTransmit Fifo MAC TransmitterData Reception Media Independent Interface MIIReceive Control Receive Inter-Frame IntervalIeee 802.3x-Based Receive Buffer Flow Control Collision-Based Receive Buffer Flow ControlCRC Insertion Transmit ControlAdaptive Performance Optimization APO Interpacket-Gap IPG EnforcementSpeed, Duplex, and Pause Frame Support Transmit Flow ControlPacket Receive Operation Receive DMA Host ConfigurationReceive Channel Enabling Receive Address MatchingHardware Receive QOS Support Host Free Buffer TrackingReceive Channel Teardown Receive Frame Classification Promiscuous Receive ModeReceive Frame Treatment Receive Frame Treatment SummaryReceive Overrun Middle of Frame Overrun TreatmentMiddle of Frame Overrun Treatment Packet Transmit Operation Transmit DMA Host ConfigurationReceive and Transmit Latency Transmit Channel TeardownReset Considerations Software Reset ConsiderationsTransfer Node Priority Initialization Hardware Reset ConsiderationsEnabling the EMAC/MDIO Peripheral Emac Control Module InitializationExample 4. Emac Control Module Initialization Code Mdio Module InitializationExample 5. Mdio Module Initialization Code Emac Module Initialization Emac Module Interrupt Events and Requests Interrupt SupportTransmit Packet Completion Interrupts Receive Packet Completion InterruptsStatistics Interrupt Host Error InterruptMdio Module Interrupt Events and Requests User Access Completion InterruptLink Change Interrupt Proper Interrupt ProcessingPower Management Emulation ConsiderationsEmulation Control Emac Control Module Registers Emac Control Module Interrupt Control Register EwctlAcronym Register Description Bit FieldEmac Control Module Interrupt Timer Count Register Ewinttcnt Mdio Version Register Version Management Data Input/Output Mdio RegistersMdio Version Register Version Field Descriptions Mdio Control Register Control Field Descriptions Mdio Control Register ControlPHY Link Status Register Link PHY Acknowledge Status Register AlivePHY Acknowledge Status Register Alive Field Descriptions PHY Link Status Register Link Field DescriptionsNo Mdio link change event Will clear the event and writing a 0 has no effect No Mdio user command complete event USERINTMASKED0 and USERINTMASKED1 correspond to USERACCESS0 WS-0 Userintmaskclear Mdio User Access Register 0 USERACCESS0 Field Descriptions Mdio User Access Register 0 USERACCESS0Linksel Linkintenb Mdio User PHY Select Register 0 USERPHYSEL0Phyadrmon Bit Field Value DescriptionMdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User Access Register 1 USERACCESS1Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1Ethernet Media Access Controller Emac Registers Offset Acronym Register Description Ethernet Media Access Controller Emac RegistersNetwork Statistics Registers Offset Acronym Register DescriptionTransmit Identification and Version Register Txidver Transmit Control Register TxcontrolTransmit Control Register Txcontrol Field Descriptions Transmit Teardown Register Txteardown Transmit Teardown Register Txteardown Field DescriptionsTxtdnch Receive Identification and Version Register Rxidver Receive Control Register RxcontrolReceive Control Register Rxcontrol Field Descriptions Receive Teardown Register Rxteardown Receive Teardown Register Rxteardown Field DescriptionsRxtdnch TX7PEND Transmit Interrupt Status Unmasked Register TxintstatrawTransmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register TxintstatmaskedTX7MASK Transmit Interrupt Mask Set Register TxintmasksetTransmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register TxintmaskclearMAC Input Vector Register Macinvector Field Descriptions MAC Input Vector Register MacinvectorUserint Linkint Hostpend Statpend Rxpend TxpendRX7PEND Receive Interrupt Status Unmasked Register RxintstatrawReceive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register RxintstatmaskedRX7MASK Receive Interrupt Mask Set Register RxintmasksetReceive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register RxintmaskclearMAC Interrupt Status Unmasked Register Macintstatraw MAC Interrupt Status Masked Register MacintstatmaskedHostpend Statpend MAC Interrupt Mask Clear Register Macintmaskclear MAC Interrupt Mask Set Register MacintmasksetHostmask Statmask HostmaskRxcmfen Rxpasscrc Rxqosen RxnochainRxcsfen Rxcefen Rxcafen RxpromchFrames containing errors are filtered Receive multicast channel select RXCH7EN Receive Unicast Enable Set Register RxunicastsetReceive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register RxunicastclearReceive Maximum Length Register Rxmaxlen Receive Buffer Offset Register RxbufferoffsetReceive Maximum Length Register Rxmaxlen Field Descriptions Reserved RX nFLOWTHRESH FFh RxfilterthreshReceive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol Field Descriptions MAC Control Register MaccontrolLoopback Sent. Full-duplex mode no outgoing pause frames are sentMAC Status Register Macstatus Field Descriptions MAC Status Register MacstatusBit Field Value Description MAC Status Register Macstatus Field DescriptionsFifo Control Register Fifocontrol Emulation Control Register EmcontrolEmulation Control Register Emcontrol Field Descriptions Fifo Control Register Fifocontrol Field DescriptionsSoft Reset Register Softreset MAC Configuration Register MacconfigMAC Configuration Register Macconfig Field Descriptions Soft Reset Register Softreset Field DescriptionsMAC Source Address High Bytes Register Macsrcaddrhi MAC Source Address Low Bytes Register MacsrcaddrloMAC Hash Address Register 2 MACHASH2 MAC Hash Address Register 1 MACHASH1MAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 2 MACHASH2 Field DescriptionsBack Off Test Register Bofftest Transmit Pacing Algorithm Test Register TpacetestBack Off Test Register Bofftest Field Descriptions Transmit Pause Timer Register Txpause Receive Pause Timer Register RxpauseReceive Pause Timer Register Rxpause Field Descriptions Transmit Pause Timer Register Txpause Field DescriptionsMAC Address Low Bytes Register Macaddrlo MAC Address High Bytes Register MacaddrhiMAC Address Low Bytes Register Macaddrlo Field Descriptions MAC Index Register Macindex MAC Index Register Macindex Field DescriptionsMacindex TX nHDP Receive Channel 0-7 Completion Pointer Register RXnCP Transmit Channel 0-7 Completion Pointer Register TXnCPGood Receive Frames Register Rxgoodframes Network Statistics RegistersBroadcast Receive Frames Register Rxbcastframes Multicast Receive Frames Register RxmcastframesReceive Alignment/Code Errors Register Rxaligncodeerrors Receive CRC Errors Register RxcrcerrorsPause Receive Frames Register Rxpauseframes Receive Oversized Frames Register RxoversizedReceive Undersized Frames Register Rxundersized Receive Jabber Frames Register RxjabberReceive Frame Fragments Register Rxfragments Filtered Receive Frames Register RxfilteredReceive QOS Filtered Frames Register Rxqosfiltered Receive Octet Frames Register RxoctetsGood Transmit Frames Register Txgoodframes Multicast Transmit Frames Register Txmcastframes Broadcast Transmit Frames Register TxbcastframesPause Transmit Frames Register Txpauseframes Deferred Transmit Frames Register TxdeferredTransmit Single Collision Frames Register Txsinglecoll Transmit Underrun Error Register TxunderrunTransmit Multiple Collision Frames Register Txmulticoll Transmit Late Collision Frames Register TxlatecollTransmit Carrier Sense Errors Register Txcarriersense Transmit Octet Frames Register TxoctetsTransmit and Receive 64 Octet Frames Register FRAME64 Network Octet Frames Register Netoctets Receive DMA Overruns Register Rxdmaoverruns Appendix a Glossary Term Definition Table A-1. Physical Layer DefinitionsReference Additions/Modifications/Deletions Table B-1. Document Revision HistoryDSP Products Applications
Related manuals
Manual 38 pages 8.14 Kb
Top Page Image Contents