Texas Instruments TMS320DM643X DMP manual List of Tables

Page 8

 

 

List of Tables

 

 

 

1

EMAC and MDIO Signals

14

 

2

Ethernet Frame Description

15

 

3

Basic Descriptor Description

17

 

4

Receive Frame Treatment Summary

42

 

5

Middle of Frame Overrun Treatment

43

 

6

Emulation Control

52

 

7

EMAC Control Module Registers

53

 

8

EMAC Control Module Interrupt Control Register (EWCTL) Field Descriptions

53

 

9

EMAC Control Module Interrupt Timer Count Register (EWINTTCNT) Field Descriptions

54

 

10

Management Data Input/Output (MDIO) Registers

55

 

11

MDIO Version Register (VERSION) Field Descriptions

55

 

12

MDIO Control Register (CONTROL) Field Descriptions

56

 

13

PHY Acknowledge Status Register (ALIVE) Field Descriptions

57

 

14

PHY Link Status Register (LINK) Field Descriptions

57

 

15

MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) Field Descriptions

58

 

16

MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) Field Descriptions

59

 

17

MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) Field Descriptions

60

 

18

MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) Field Descriptions

61

 

19

MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) Field Descriptions

62

 

20

MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) Field

 

 

 

Descriptions

63

 

21

MDIO User Access Register 0 (USERACCESS0) Field Descriptions

64

 

22

MDIO User PHY Select Register 0 (USERPHYSEL0) Field Descriptions

65

 

23

MDIO User Access Register 1 (USERACCESS1) Field Descriptions

66

 

24

MDIO User PHY Select Register 1 (USERPHYSEL1) Field Descriptions

67

 

25

Ethernet Media Access Controller (EMAC) Registers

68

 

26

Transmit Identification and Version Register (TXIDVER) Field Descriptions

71

 

27

Transmit Control Register (TXCONTROL) Field Descriptions

71

 

28

Transmit Teardown Register (TXTEARDOWN) Field Descriptions

72

 

29

Receive Identification and Version Register (RXIDVER) Field Descriptions

73

 

30

Receive Control Register (RXCONTROL) Field Descriptions

73

 

31

Receive Teardown Register (RXTEARDOWN) Field Descriptions

74

 

32

Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions

75

 

33

Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions

76

 

34

Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions

77

 

35

Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions

78

 

36

MAC Input Vector Register (MACINVECTOR) Field Descriptions

79

 

37

Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions

80

 

38

Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions

81

 

39

Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions

82

 

40

Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions

83

 

41

MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions

84

 

42

MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions

84

 

43

MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions

85

 

44

MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions

85

 

45

Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions .

86

 

46

Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions

89

 

47

Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions

90

 

48

Receive Maximum Length Register (RXMAXLEN) Field Descriptions

91

 

49

Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions

91

8

List of Tables

SPRU941A –April 2007

Page 7 Page 9
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Page 7 Page 9
Contents Users Guide Submit Documentation Feedback Contents MAC Hash Address Register 1 MACHASH1 Appendix a Appendix BList of Figures Transmit Pacing Algorithm Test Register Tpacetest List of Tables Fifo Control Register Fifocontrol Field Descriptions Read This First Features Purpose of the PeripheralFunctional Block Diagram Emac and Mdio Block DiagramSignal Descriptions Industry Standards Compliance StatementClock Control Memory MapEmac and Mdio Signals Signal Type DescriptionEthernet Protocol Overview Ethernet Frame FormatEthernet Frame Description Field Bytes DescriptionPacket Buffer Descriptors Ethernet’s Multiple Access ProtocolProgramming Interface Basic Descriptor Description Typical Descriptor Linked ListTransmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Transmit Buffer Descriptor Format Example 1. Transmit Buffer Descriptor in C Structure FormatNext Descriptor Pointer Buffer PointerBuffer Offset Buffer LengthEnd of Packet EOP Flag Ownership Owner FlagEnd of Queue EOQ Flag Teardown Complete Tdowncmplt FlagReceive Buffer Descriptor Format Receive Buffer Descriptor FormatExample 2. Receive Buffer Descriptor in C Structure Format #define EmacdscflagjabberBuffer Length Code Error Codeerror Flag Alignment Error Alignerror FlagCRC Error Crcerror Flag Jabber FlagEmac Control Module No Match Nomatch FlagInternal Memory Bus ArbiterMdio Module Components Mdio ModuleInterrupt Control PHY Register User Access Mdio Clock GeneratorGlobal PHY Detection and Link State Monitoring Active PHY MonitoringMdio Module Operational Overview Reading Data From a PHY Register Initializing the Mdio ModuleWriting Data To a PHY Register Example of Mdio Register Access Code Example 3. Mdio Register Access MacrosEmac Module Emac Module ComponentsReceive DMA Engine Receive FifoClock and Reset Logic Transmit DMA EngineTransmit Fifo MAC TransmitterMedia Independent Interface MII Data ReceptionReceive Control Receive Inter-Frame IntervalCollision-Based Receive Buffer Flow Control Ieee 802.3x-Based Receive Buffer Flow ControlTransmit Control CRC InsertionAdaptive Performance Optimization APO Interpacket-Gap IPG EnforcementTransmit Flow Control Speed, Duplex, and Pause Frame SupportReceive DMA Host Configuration Packet Receive OperationReceive Channel Enabling Receive Address MatchingReceive Channel Teardown Hardware Receive QOS SupportHost Free Buffer Tracking Promiscuous Receive Mode Receive Frame ClassificationReceive Frame Treatment Summary Receive Frame TreatmentMiddle of Frame Overrun Treatment Receive OverrunMiddle of Frame Overrun Treatment Transmit DMA Host Configuration Packet Transmit OperationReceive and Transmit Latency Transmit Channel TeardownTransfer Node Priority Reset ConsiderationsSoftware Reset Considerations Hardware Reset Considerations InitializationEnabling the EMAC/MDIO Peripheral Emac Control Module InitializationExample 5. Mdio Module Initialization Code Example 4. Emac Control Module Initialization CodeMdio Module Initialization Emac Module Initialization Interrupt Support Emac Module Interrupt Events and RequestsTransmit Packet Completion Interrupts Receive Packet Completion InterruptsHost Error Interrupt Statistics InterruptUser Access Completion Interrupt Mdio Module Interrupt Events and RequestsLink Change Interrupt Proper Interrupt ProcessingEmulation Control Power ManagementEmulation Considerations Emac Control Module Interrupt Control Register Ewctl Emac Control Module RegistersAcronym Register Description Bit FieldEmac Control Module Interrupt Timer Count Register Ewinttcnt Mdio Version Register Version Field Descriptions Mdio Version Register VersionManagement Data Input/Output Mdio Registers Mdio Control Register Control Mdio Control Register Control Field DescriptionsPHY Acknowledge Status Register Alive PHY Link Status Register LinkPHY Acknowledge Status Register Alive Field Descriptions PHY Link Status Register Link Field DescriptionsNo Mdio link change event Will clear the event and writing a 0 has no effect No Mdio user command complete event USERINTMASKED0 and USERINTMASKED1 correspond to USERACCESS0 WS-0 Userintmaskclear Mdio User Access Register 0 USERACCESS0 Mdio User Access Register 0 USERACCESS0 Field DescriptionsMdio User PHY Select Register 0 USERPHYSEL0 Linksel LinkintenbPhyadrmon Bit Field Value DescriptionMdio User Access Register 1 USERACCESS1 Mdio User Access Register 1 USERACCESS1 Field DescriptionsMdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1Ethernet Media Access Controller Emac Registers Ethernet Media Access Controller Emac Registers Offset Acronym Register DescriptionOffset Acronym Register Description Network Statistics RegistersTransmit Control Register Txcontrol Field Descriptions Transmit Identification and Version Register TxidverTransmit Control Register Txcontrol Txtdnch Transmit Teardown Register TxteardownTransmit Teardown Register Txteardown Field Descriptions Receive Control Register Rxcontrol Field Descriptions Receive Identification and Version Register RxidverReceive Control Register Rxcontrol Rxtdnch Receive Teardown Register RxteardownReceive Teardown Register Rxteardown Field Descriptions Transmit Interrupt Status Unmasked Register Txintstatraw TX7PENDTransmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register TxintstatmaskedTransmit Interrupt Mask Set Register Txintmaskset TX7MASKTransmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register TxintmaskclearMAC Input Vector Register Macinvector MAC Input Vector Register Macinvector Field DescriptionsUserint Linkint Hostpend Statpend Rxpend TxpendReceive Interrupt Status Unmasked Register Rxintstatraw RX7PENDReceive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register RxintstatmaskedReceive Interrupt Mask Set Register Rxintmaskset RX7MASKReceive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register RxintmaskclearHostpend Statpend MAC Interrupt Status Unmasked Register MacintstatrawMAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Mask Set Register Macintmaskset MAC Interrupt Mask Clear Register MacintmaskclearHostmask Statmask HostmaskRxpasscrc Rxqosen Rxnochain RxcmfenRxcsfen Rxcefen Rxcafen RxpromchFrames containing errors are filtered Receive multicast channel select Receive Unicast Enable Set Register Rxunicastset RXCH7ENReceive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register RxunicastclearReceive Maximum Length Register Rxmaxlen Field Descriptions Receive Maximum Length Register RxmaxlenReceive Buffer Offset Register Rxbufferoffset Rxfilterthresh Reserved RX nFLOWTHRESH FFhReceive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol MAC Control Register Maccontrol Field DescriptionsSent. Full-duplex mode no outgoing pause frames are sent LoopbackMAC Status Register Macstatus MAC Status Register Macstatus Field DescriptionsMAC Status Register Macstatus Field Descriptions Bit Field Value DescriptionEmulation Control Register Emcontrol Fifo Control Register FifocontrolEmulation Control Register Emcontrol Field Descriptions Fifo Control Register Fifocontrol Field DescriptionsMAC Configuration Register Macconfig Soft Reset Register SoftresetMAC Configuration Register Macconfig Field Descriptions Soft Reset Register Softreset Field DescriptionsMAC Source Address Low Bytes Register Macsrcaddrlo MAC Source Address High Bytes Register MacsrcaddrhiMAC Hash Address Register 1 MACHASH1 MAC Hash Address Register 2 MACHASH2MAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 2 MACHASH2 Field DescriptionsBack Off Test Register Bofftest Field Descriptions Back Off Test Register BofftestTransmit Pacing Algorithm Test Register Tpacetest Receive Pause Timer Register Rxpause Transmit Pause Timer Register TxpauseReceive Pause Timer Register Rxpause Field Descriptions Transmit Pause Timer Register Txpause Field DescriptionsMAC Address Low Bytes Register Macaddrlo Field Descriptions MAC Address Low Bytes Register MacaddrloMAC Address High Bytes Register Macaddrhi Macindex MAC Index Register MacindexMAC Index Register Macindex Field Descriptions TX nHDP Transmit Channel 0-7 Completion Pointer Register TXnCP Receive Channel 0-7 Completion Pointer Register RXnCPNetwork Statistics Registers Good Receive Frames Register RxgoodframesBroadcast Receive Frames Register Rxbcastframes Multicast Receive Frames Register RxmcastframesReceive CRC Errors Register Rxcrcerrors Receive Alignment/Code Errors Register RxaligncodeerrorsPause Receive Frames Register Rxpauseframes Receive Oversized Frames Register RxoversizedReceive Jabber Frames Register Rxjabber Receive Undersized Frames Register RxundersizedReceive Frame Fragments Register Rxfragments Filtered Receive Frames Register RxfilteredGood Transmit Frames Register Txgoodframes Receive QOS Filtered Frames Register RxqosfilteredReceive Octet Frames Register Rxoctets Broadcast Transmit Frames Register Txbcastframes Multicast Transmit Frames Register TxmcastframesPause Transmit Frames Register Txpauseframes Deferred Transmit Frames Register TxdeferredTransmit Underrun Error Register Txunderrun Transmit Single Collision Frames Register TxsinglecollTransmit Multiple Collision Frames Register Txmulticoll Transmit Late Collision Frames Register TxlatecollTransmit and Receive 64 Octet Frames Register FRAME64 Transmit Carrier Sense Errors Register TxcarriersenseTransmit Octet Frames Register Txoctets Network Octet Frames Register Netoctets Receive DMA Overruns Register Rxdmaoverruns Appendix a Glossary Table A-1. Physical Layer Definitions Term DefinitionTable B-1. Document Revision History Reference Additions/Modifications/DeletionsProducts Applications DSP
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