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Ethernet Media Access Controller (EMAC) Registers
5.7Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)
The transmit interrupt status (unmasked) register (TXINTSTATRAW) is shown in Figure 33 and described in Table 32.
| Figure 33. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) |
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31 |
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| 16 |
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| Reserved |
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15 |
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| 8 |
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| Reserved |
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX7PEND | TX6PEND | TX5PEND | TX4PEND | TX3PEND | TX2PEND | TX1PEND | TX0PEND |
LEGEND: R = Read only;
Table 32. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions
Bit | Field | Value | Description |
Reserved | 0 | Reserved | |
7 | TX7PEND | TX7PEND raw interrupt read (before mask) | |
6 | TX6PEND | TX6PEND raw interrupt read (before mask) | |
5 | TX5PEND | TX5PEND raw interrupt read (before mask) | |
4 | TX4PEND | TX4PEND raw interrupt read (before mask) | |
3 | TX3PEND | TX3PEND raw interrupt read (before mask) | |
2 | TX2PEND | TX2PEND raw interrupt read (before mask) | |
1 | TX1PEND | TX1PEND raw interrupt read (before mask) | |
0 | TX0PEND | TX0PEND raw interrupt read (before mask) |
SPRU941A
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