Texas Instruments TMS320DM643X DMP manual Receive Overrun, Middle of Frame Overrun Treatment

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Peripheral Architecture

2.10.9Receive Overrun

The types of receive overrun are:

∙FIFO start of frame overrun (FIFO_SOF)

∙FIFO middle of frame overrun (FIFO_MOF)

∙DMA start of frame overrun (DMA_SOF)

∙DMA middle of frame overrun (DMA_MOF)

The statistics counters used to track these types of receive overrun are:

∙Receive start of frame overruns register (RXSOFOVERRUNS)

∙Receive middle of frame overruns register (RXMOFOVERRUNS)

∙Receive DMA overruns register (RXDMAOVERRUNS)

Start of frame overruns happen when there are no resources available when frame reception begins. Start of frame overruns increment the appropriate overrun statistic(s) and the frame is filtered.

Middle of frame overruns happen when there are some resources to start the frame reception, but the resources run out during frame reception. In normal operation, a frame that overruns after starting the frame reception is filtered and the appropriate statistic(s) are incremented; however, the RXCEFEN bit in the receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE) affects overrun frame treatment. Table 5 shows how the overrun condition is handled for the middle of frame overrun.

Table 5. Middle of Frame Overrun Treatment

Address Match	RXCAFEN	RXCEFEN	Middle of Frame Overrun Treatment
0	0	X	Overrun frame filtered.
0	1	0	Overrun frame filtered.
0	1	1	As much frame data as possible is transferred to the promiscuous channel
			until overrun. The appropriate overrun statistic(s) is incremented and the
			OVERRUN and NOMATCH flags are set in the SOP buffer descriptor. Note
			that the RXMAXLEN number of bytes cannot be reached for an overrun to
			occur (it would be truncated and be a jabber or oversize).
1	X	0	Overrun frame filtered with the appropriate overrun statistic(s) incremented.
1	X	1	As much frame data as possible is transferred to the address match
			channel until overrun. The appropriate overrun statistic(s) is incremented
			and the OVERRUN flag is set in the SOP buffer descriptor. Note that the
			RXMAXLEN number of bytes cannot be reached for an overrun to occur (it
			would be truncated).

SPRU941A –April 2007Ethernet Media Access Controller (EMAC)/ 43

Submit Documentation Feedback	Management Data Input/Output (MDIO)

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Contents Users Guide Submit Documentation Feedback Contents MAC Hash Address Register 1 MACHASH1 Appendix B Appendix aList of Figures Transmit Pacing Algorithm Test Register Tpacetest List of Tables Fifo Control Register Fifocontrol Field Descriptions Read This First Purpose of the Peripheral FeaturesEmac and Mdio Block Diagram Functional Block DiagramMemory Map Signal DescriptionsIndustry Standards Compliance Statement Clock ControlSignal Type Description Emac and Mdio SignalsField Bytes Description Ethernet Protocol OverviewEthernet Frame Format Ethernet Frame DescriptionProgramming Interface Ethernet’s Multiple Access ProtocolPacket Buffer Descriptors Typical Descriptor Linked List Basic Descriptor DescriptionTransmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Example 1. Transmit Buffer Descriptor in C Structure Format Transmit Buffer Descriptor FormatBuffer Length Next Descriptor PointerBuffer Pointer Buffer OffsetTeardown Complete Tdowncmplt Flag End of Packet EOP FlagOwnership Owner Flag End of Queue EOQ FlagReceive Buffer Descriptor Format Receive Buffer Descriptor Format#define Emacdscflagjabber Example 2. Receive Buffer Descriptor in C Structure FormatBuffer Length Jabber Flag Code Error Codeerror FlagAlignment Error Alignerror Flag CRC Error Crcerror FlagBus Arbiter Emac Control ModuleNo Match Nomatch Flag Internal MemoryInterrupt Control Mdio ModuleMdio Module Components Active PHY Monitoring PHY Register User AccessMdio Clock Generator Global PHY Detection and Link State MonitoringMdio Module Operational Overview Writing Data To a PHY Register Initializing the Mdio ModuleReading Data From a PHY Register Example 3. Mdio Register Access Macros Example of Mdio Register Access CodeReceive Fifo Emac ModuleEmac Module Components Receive DMA EngineMAC Transmitter Clock and Reset LogicTransmit DMA Engine Transmit FifoReceive Inter-Frame Interval Media Independent Interface MIIData Reception Receive ControlIeee 802.3x-Based Receive Buffer Flow Control Collision-Based Receive Buffer Flow ControlInterpacket-Gap IPG Enforcement Transmit ControlCRC Insertion Adaptive Performance Optimization APOSpeed, Duplex, and Pause Frame Support Transmit Flow ControlReceive Address Matching Receive DMA Host ConfigurationPacket Receive Operation Receive Channel EnablingHost Free Buffer Tracking Hardware Receive QOS SupportReceive Channel Teardown Receive Frame Classification Promiscuous Receive ModeReceive Frame Treatment Receive Frame Treatment SummaryMiddle of Frame Overrun Treatment Receive OverrunMiddle of Frame Overrun Treatment Transmit Channel Teardown Transmit DMA Host ConfigurationPacket Transmit Operation Receive and Transmit LatencySoftware Reset Considerations Reset ConsiderationsTransfer Node Priority Emac Control Module Initialization Hardware Reset ConsiderationsInitialization Enabling the EMAC/MDIO PeripheralMdio Module Initialization Example 4. Emac Control Module Initialization CodeExample 5. Mdio Module Initialization Code Emac Module Initialization Receive Packet Completion Interrupts Interrupt SupportEmac Module Interrupt Events and Requests Transmit Packet Completion InterruptsStatistics Interrupt Host Error InterruptProper Interrupt Processing User Access Completion InterruptMdio Module Interrupt Events and Requests Link Change InterruptEmulation Considerations Power ManagementEmulation Control Bit Field Emac Control Module Interrupt Control Register EwctlEmac Control Module Registers Acronym Register DescriptionEmac Control Module Interrupt Timer Count Register Ewinttcnt Management Data Input/Output Mdio Registers Mdio Version Register VersionMdio Version Register Version Field Descriptions Mdio Control Register Control Field Descriptions Mdio Control Register ControlPHY Link Status Register Link Field Descriptions PHY Acknowledge Status Register AlivePHY Link Status Register Link PHY Acknowledge Status Register Alive Field DescriptionsNo Mdio link change event Will clear the event and writing a 0 has no effect No Mdio user command complete event USERINTMASKED0 and USERINTMASKED1 correspond to USERACCESS0 WS-0 Userintmaskclear Mdio User Access Register 0 USERACCESS0 Field Descriptions Mdio User Access Register 0 USERACCESS0Bit Field Value Description Mdio User PHY Select Register 0 USERPHYSEL0Linksel Linkintenb PhyadrmonMdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User Access Register 1 USERACCESS1Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1Ethernet Media Access Controller Emac Registers Offset Acronym Register Description Ethernet Media Access Controller Emac RegistersNetwork Statistics Registers Offset Acronym Register DescriptionTransmit Control Register Txcontrol Transmit Identification and Version Register TxidverTransmit Control Register Txcontrol Field Descriptions Transmit Teardown Register Txteardown Field Descriptions Transmit Teardown Register TxteardownTxtdnch Receive Control Register Rxcontrol Receive Identification and Version Register RxidverReceive Control Register Rxcontrol Field Descriptions Receive Teardown Register Rxteardown Field Descriptions Receive Teardown Register RxteardownRxtdnch TX7PEND Transmit Interrupt Status Unmasked Register TxintstatrawTransmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register TxintstatmaskedTX7MASK Transmit Interrupt Mask Set Register TxintmasksetTransmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register TxintmaskclearHostpend Statpend Rxpend Txpend MAC Input Vector Register MacinvectorMAC Input Vector Register Macinvector Field Descriptions Userint LinkintRX7PEND Receive Interrupt Status Unmasked Register RxintstatrawReceive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register RxintstatmaskedRX7MASK Receive Interrupt Mask Set Register RxintmasksetReceive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register RxintmaskclearMAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Status Unmasked Register MacintstatrawHostpend Statpend Hostmask MAC Interrupt Mask Set Register MacintmasksetMAC Interrupt Mask Clear Register Macintmaskclear Hostmask StatmaskRxpromch Rxpasscrc Rxqosen RxnochainRxcmfen Rxcsfen Rxcefen RxcafenFrames containing errors are filtered Receive multicast channel select RXCH7EN Receive Unicast Enable Set Register RxunicastsetReceive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register RxunicastclearReceive Buffer Offset Register Rxbufferoffset Receive Maximum Length Register RxmaxlenReceive Maximum Length Register Rxmaxlen Field Descriptions Reserved RX nFLOWTHRESH FFh RxfilterthreshReceive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol Field Descriptions MAC Control Register MaccontrolLoopback Sent. Full-duplex mode no outgoing pause frames are sentMAC Status Register Macstatus Field Descriptions MAC Status Register MacstatusBit Field Value Description MAC Status Register Macstatus Field DescriptionsFifo Control Register Fifocontrol Field Descriptions Emulation Control Register EmcontrolFifo Control Register Fifocontrol Emulation Control Register Emcontrol Field DescriptionsSoft Reset Register Softreset Field Descriptions MAC Configuration Register MacconfigSoft Reset Register Softreset MAC Configuration Register Macconfig Field DescriptionsMAC Source Address High Bytes Register Macsrcaddrhi MAC Source Address Low Bytes Register MacsrcaddrloMAC Hash Address Register 2 MACHASH2 Field Descriptions MAC Hash Address Register 1 MACHASH1MAC Hash Address Register 2 MACHASH2 MAC Hash Address Register 1 MACHASH1 Field DescriptionsTransmit Pacing Algorithm Test Register Tpacetest Back Off Test Register BofftestBack Off Test Register Bofftest Field Descriptions Transmit Pause Timer Register Txpause Field Descriptions Receive Pause Timer Register RxpauseTransmit Pause Timer Register Txpause Receive Pause Timer Register Rxpause Field DescriptionsMAC Address High Bytes Register Macaddrhi MAC Address Low Bytes Register MacaddrloMAC Address Low Bytes Register Macaddrlo Field Descriptions MAC Index Register Macindex Field Descriptions MAC Index Register MacindexMacindex TX nHDP Receive Channel 0-7 Completion Pointer Register RXnCP Transmit Channel 0-7 Completion Pointer Register TXnCPMulticast Receive Frames Register Rxmcastframes Network Statistics RegistersGood Receive Frames Register Rxgoodframes Broadcast Receive Frames Register RxbcastframesReceive Oversized Frames Register Rxoversized Receive CRC Errors Register RxcrcerrorsReceive Alignment/Code Errors Register Rxaligncodeerrors Pause Receive Frames Register RxpauseframesFiltered Receive Frames Register Rxfiltered Receive Jabber Frames Register RxjabberReceive Undersized Frames Register Rxundersized Receive Frame Fragments Register RxfragmentsReceive Octet Frames Register Rxoctets Receive QOS Filtered Frames Register RxqosfilteredGood Transmit Frames Register Txgoodframes Deferred Transmit Frames Register Txdeferred Broadcast Transmit Frames Register TxbcastframesMulticast Transmit Frames Register Txmcastframes Pause Transmit Frames Register TxpauseframesTransmit Late Collision Frames Register Txlatecoll Transmit Underrun Error Register TxunderrunTransmit Single Collision Frames Register Txsinglecoll Transmit Multiple Collision Frames Register TxmulticollTransmit Octet Frames Register Txoctets Transmit Carrier Sense Errors Register TxcarriersenseTransmit and Receive 64 Octet Frames Register FRAME64 Network Octet Frames Register Netoctets Receive DMA Overruns Register Rxdmaoverruns Appendix a Glossary Term Definition Table A-1. Physical Layer DefinitionsReference Additions/Modifications/Deletions Table B-1. Document Revision HistoryDSP Products Applications

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