www.ti.com
Ethernet Media Access Controller (EMAC) Registers
5.21 Receive Unicast Enable Set Register (RXUNICASTSET)
The receive unicast enable set register (RXUNICASTSET) is shown in Figure 47 and described in Table 46.
| Figure 47. Receive Unicast Enable Set Register (RXUNICASTSET) |
| |||||
31 |
|
|
|
|
|
| 16 |
|
|
| Reserved |
|
|
| |
|
|
|
|
|
|
| |
15 |
|
|
|
|
|
| 8 |
|
|
| Reserved |
|
|
| |
|
|
|
|
|
|
| |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXCH7EN | RXCH6EN | RXCH5EN | RXCH4EN | RXCH3EN | RXCH2EN | RXCH1EN | RXCH0EN |
|
LEGEND: R = Read only; R/W = Read/Write; WS = Write 1 to set, write of 0 has no effect;
Table 46. Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions
Bit | Field | Value | Description |
Reserved | 0 | Reserved | |
7 | RXCH7EN | Receive channel 7 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. | |
|
|
| May be read. |
6 | RXCH6EN | Receive channel 6 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. | |
|
|
| May be read. |
5 | RXCH5EN | Receive channel 5 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. | |
|
|
| May be read. |
4 | RXCH4EN | Receive channel 4 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. | |
|
|
| May be read. |
3 | RXCH3EN | Receive channel 3 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. | |
|
|
| May be read. |
2 | RXCH2EN | Receive channel 2 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. | |
|
|
| May be read. |
1 | RXCH1EN | Receive channel 1 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. | |
|
|
| May be read. |
0 | RXCH0EN | Receive channel 0 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. | |
|
|
| May be read. |
SPRU941A
Submit Documentation Feedback | Management Data Input/Output (MDIO) |
|