Texas Instruments TMS320DM643X DMP manual Ethernet Media Access Controller Emac Registers

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Ethernet Media Access Controller (EMAC) Registers

 

Table 25. Ethernet Media Access Controller (EMAC) Registers (continued)

 

Offset

Acronym

Register Description

Section

168h

EMCONTROL

Emulation Control Register

Section 5.30

16Ch

FIFOCONTROL

FIFO Control Register

Section 5.31

170h

MACCONFIG

MAC Configuration Register

Section 5.32

174h

SOFTRESET

Soft Reset Register

Section 5.33

1D0h

MACSRCADDRLO

MAC Source Address Low Bytes Register

Section 5.34

1D4h

MACSRCADDRHI

MAC Source Address High Bytes Register

Section 5.35

1D8h

MACHASH1

MAC Hash Address Register 1

Section 5.36

1DCh

MACHASH2

MAC Hash Address Register 2

Section 5.37

1E0h

BOFFTEST

Back Off Test Register

Section 5.38

1E4h

TPACETEST

Transmit Pacing Algorithm Test Register

Section 5.39

1E8h

RXPAUSE

Receive Pause Timer Register

Section 5.40

1ECh

TXPAUSE

Transmit Pause Timer Register

Section 5.41

500h

MACADDRLO

MAC Address Low Bytes Register, Used in Receive Address Matching

Section 5.42

504h

MACADDRHI

MAC Address High Bytes Register, Used in Receive Address Matching

Section 5.43

508h

MACINDEX

MAC Index Register

Section 5.44

600h

TX0HDP

Transmit Channel 0 DMA Head Descriptor Pointer Register

Section 5.45

604h

TX1HDP

Transmit Channel 1 DMA Head Descriptor Pointer Register

Section 5.45

608h

TX2HDP

Transmit Channel 2 DMA Head Descriptor Pointer Register

Section 5.45

60Ch

TX3HDP

Transmit Channel 3 DMA Head Descriptor Pointer Register

Section 5.45

610h

TX4HDP

Transmit Channel 4 DMA Head Descriptor Pointer Register

Section 5.45

614h

TX5HDP

Transmit Channel 5 DMA Head Descriptor Pointer Register

Section 5.45

618h

TX6HDP

Transmit Channel 6 DMA Head Descriptor Pointer Register

Section 5.45

61Ch

TX7HDP

Transmit Channel 7 DMA Head Descriptor Pointer Register

Section 5.45

620h

RX0HDP

Receive Channel 0 DMA Head Descriptor Pointer Register

Section 5.46

624h

RX1HDP

Receive Channel 1 DMA Head Descriptor Pointer Register

Section 5.46

628h

RX2HDP

Receive Channel 2 DMA Head Descriptor Pointer Register

Section 5.46

62Ch

RX3HDP

Receive Channel 3 DMA Head Descriptor Pointer Register

Section 5.46

630h

RX4HDP

Receive Channel 4 DMA Head Descriptor Pointer Register

Section 5.46

634h

RX5HDP

Receive Channel 5 DMA Head Descriptor Pointer Register

Section 5.46

638h

RX6HDP

Receive Channel 6 DMA Head Descriptor Pointer Register

Section 5.46

63Ch

RX7HDP

Receive Channel 7 DMA Head Descriptor Pointer Register

Section 5.46

640h

TX0CP

Transmit Channel 0 Completion Pointer Register

Section 5.47

644h

TX1CP

Transmit Channel 1 Completion Pointer Register

Section 5.47

648h

TX2CP

Transmit Channel 2 Completion Pointer Register

Section 5.47

64Ch

TX3CP

Transmit Channel 3 Completion Pointer Register

Section 5.47

650h

TX4CP

Transmit Channel 4 Completion Pointer Register

Section 5.47

654h

TX5CP

Transmit Channel 5 Completion Pointer Register

Section 5.47

658h

TX6CP

Transmit Channel 6 Completion Pointer Register

Section 5.47

65Ch

TX7CP

Transmit Channel 7 Completion Pointer Register

Section 5.47

660h

RX0CP

Receive Channel 0 Completion Pointer Register

Section 5.48

664h

RX1CP

Receive Channel 1 Completion Pointer Register

Section 5.48

668h

RX2CP

Receive Channel 2 Completion Pointer Register

Section 5.48

66Ch

RX3CP

Receive Channel 3 Completion Pointer Register

Section 5.48

670h

RX4CP

Receive Channel 4 Completion Pointer Register

Section 5.48

674h

RX5CP

Receive Channel 5 Completion Pointer Register

Section 5.48

678h

RX6CP

Receive Channel 6 Completion Pointer Register

Section 5.48

SPRU941A –April 2007Ethernet Media Access Controller (EMAC)/ 69

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Management Data Input/Output (MDIO)

 

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Contents Users Guide Submit Documentation Feedback Contents MAC Hash Address Register 1 MACHASH1 Appendix B Appendix aList of Figures Transmit Pacing Algorithm Test Register Tpacetest List of Tables Fifo Control Register Fifocontrol Field Descriptions Read This First Purpose of the Peripheral FeaturesEmac and Mdio Block Diagram Functional Block DiagramIndustry Standards Compliance Statement Signal DescriptionsClock Control Memory MapSignal Type Description Emac and Mdio SignalsEthernet Frame Format Ethernet Protocol OverviewEthernet Frame Description Field Bytes DescriptionEthernet’s Multiple Access Protocol Programming InterfacePacket Buffer Descriptors Typical Descriptor Linked List Basic Descriptor DescriptionTransmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Example 1. Transmit Buffer Descriptor in C Structure Format Transmit Buffer Descriptor FormatBuffer Pointer Next Descriptor PointerBuffer Offset Buffer LengthOwnership Owner Flag End of Packet EOP FlagEnd of Queue EOQ Flag Teardown Complete Tdowncmplt FlagReceive Buffer Descriptor Format Receive Buffer Descriptor Format#define Emacdscflagjabber Example 2. Receive Buffer Descriptor in C Structure FormatBuffer Length Alignment Error Alignerror Flag Code Error Codeerror FlagCRC Error Crcerror Flag Jabber FlagNo Match Nomatch Flag Emac Control ModuleInternal Memory Bus ArbiterMdio Module Interrupt ControlMdio Module Components Mdio Clock Generator PHY Register User AccessGlobal PHY Detection and Link State Monitoring Active PHY MonitoringMdio Module Operational Overview Initializing the Mdio Module Writing Data To a PHY RegisterReading Data From a PHY Register Example 3. Mdio Register Access Macros Example of Mdio Register Access CodeEmac Module Components Emac ModuleReceive DMA Engine Receive FifoTransmit DMA Engine Clock and Reset LogicTransmit Fifo MAC TransmitterData Reception Media Independent Interface MIIReceive Control Receive Inter-Frame IntervalIeee 802.3x-Based Receive Buffer Flow Control Collision-Based Receive Buffer Flow ControlCRC Insertion Transmit ControlAdaptive Performance Optimization APO Interpacket-Gap IPG EnforcementSpeed, Duplex, and Pause Frame Support Transmit Flow ControlPacket Receive Operation Receive DMA Host ConfigurationReceive Channel Enabling Receive Address MatchingHardware Receive QOS Support Host Free Buffer TrackingReceive Channel Teardown Receive Frame Classification Promiscuous Receive ModeReceive Frame Treatment Receive Frame Treatment SummaryReceive Overrun Middle of Frame Overrun TreatmentMiddle of Frame Overrun Treatment Packet Transmit Operation Transmit DMA Host ConfigurationReceive and Transmit Latency Transmit Channel TeardownReset Considerations Software Reset ConsiderationsTransfer Node Priority Initialization Hardware Reset ConsiderationsEnabling the EMAC/MDIO Peripheral Emac Control Module InitializationExample 4. Emac Control Module Initialization Code Mdio Module InitializationExample 5. Mdio Module Initialization Code Emac Module Initialization Emac Module Interrupt Events and Requests Interrupt SupportTransmit Packet Completion Interrupts Receive Packet Completion InterruptsStatistics Interrupt Host Error InterruptMdio Module Interrupt Events and Requests User Access Completion InterruptLink Change Interrupt Proper Interrupt ProcessingPower Management Emulation ConsiderationsEmulation Control Emac Control Module Registers Emac Control Module Interrupt Control Register EwctlAcronym Register Description Bit FieldEmac Control Module Interrupt Timer Count Register Ewinttcnt Mdio Version Register Version Management Data Input/Output Mdio RegistersMdio Version Register Version Field Descriptions Mdio Control Register Control Field Descriptions Mdio Control Register ControlPHY Link Status Register Link PHY Acknowledge Status Register AlivePHY Acknowledge Status Register Alive Field Descriptions PHY Link Status Register Link Field DescriptionsNo Mdio link change event Will clear the event and writing a 0 has no effect No Mdio user command complete event USERINTMASKED0 and USERINTMASKED1 correspond to USERACCESS0 WS-0 Userintmaskclear Mdio User Access Register 0 USERACCESS0 Field Descriptions Mdio User Access Register 0 USERACCESS0Linksel Linkintenb Mdio User PHY Select Register 0 USERPHYSEL0Phyadrmon Bit Field Value DescriptionMdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User Access Register 1 USERACCESS1Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1Ethernet Media Access Controller Emac Registers Offset Acronym Register Description Ethernet Media Access Controller Emac RegistersNetwork Statistics Registers Offset Acronym Register DescriptionTransmit Identification and Version Register Txidver Transmit Control Register TxcontrolTransmit Control Register Txcontrol Field Descriptions Transmit Teardown Register Txteardown Transmit Teardown Register Txteardown Field DescriptionsTxtdnch Receive Identification and Version Register Rxidver Receive Control Register RxcontrolReceive Control Register Rxcontrol Field Descriptions Receive Teardown Register Rxteardown Receive Teardown Register Rxteardown Field DescriptionsRxtdnch TX7PEND Transmit Interrupt Status Unmasked Register TxintstatrawTransmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register TxintstatmaskedTX7MASK Transmit Interrupt Mask Set Register TxintmasksetTransmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register TxintmaskclearMAC Input Vector Register Macinvector Field Descriptions MAC Input Vector Register MacinvectorUserint Linkint Hostpend Statpend Rxpend TxpendRX7PEND Receive Interrupt Status Unmasked Register RxintstatrawReceive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register RxintstatmaskedRX7MASK Receive Interrupt Mask Set Register RxintmasksetReceive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register RxintmaskclearMAC Interrupt Status Unmasked Register Macintstatraw MAC Interrupt Status Masked Register MacintstatmaskedHostpend Statpend MAC Interrupt Mask Clear Register Macintmaskclear MAC Interrupt Mask Set Register MacintmasksetHostmask Statmask HostmaskRxcmfen Rxpasscrc Rxqosen RxnochainRxcsfen Rxcefen Rxcafen RxpromchFrames containing errors are filtered Receive multicast channel select RXCH7EN Receive Unicast Enable Set Register RxunicastsetReceive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register RxunicastclearReceive Maximum Length Register Rxmaxlen Receive Buffer Offset Register RxbufferoffsetReceive Maximum Length Register Rxmaxlen Field Descriptions Reserved RX nFLOWTHRESH FFh RxfilterthreshReceive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol Field Descriptions MAC Control Register MaccontrolLoopback Sent. Full-duplex mode no outgoing pause frames are sentMAC Status Register Macstatus Field Descriptions MAC Status Register MacstatusBit Field Value Description MAC Status Register Macstatus Field DescriptionsFifo Control Register Fifocontrol Emulation Control Register EmcontrolEmulation Control Register Emcontrol Field Descriptions Fifo Control Register Fifocontrol Field DescriptionsSoft Reset Register Softreset MAC Configuration Register MacconfigMAC Configuration Register Macconfig Field Descriptions Soft Reset Register Softreset Field DescriptionsMAC Source Address High Bytes Register Macsrcaddrhi MAC Source Address Low Bytes Register MacsrcaddrloMAC Hash Address Register 2 MACHASH2 MAC Hash Address Register 1 MACHASH1MAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 2 MACHASH2 Field DescriptionsBack Off Test Register Bofftest Transmit Pacing Algorithm Test Register TpacetestBack Off Test Register Bofftest Field Descriptions Transmit Pause Timer Register Txpause Receive Pause Timer Register RxpauseReceive Pause Timer Register Rxpause Field Descriptions Transmit Pause Timer Register Txpause Field DescriptionsMAC Address Low Bytes Register Macaddrlo MAC Address High Bytes Register MacaddrhiMAC Address Low Bytes Register Macaddrlo Field Descriptions MAC Index Register Macindex MAC Index Register Macindex Field DescriptionsMacindex TX nHDP Receive Channel 0-7 Completion Pointer Register RXnCP Transmit Channel 0-7 Completion Pointer Register TXnCPGood Receive Frames Register Rxgoodframes Network Statistics RegistersBroadcast Receive Frames Register Rxbcastframes Multicast Receive Frames Register RxmcastframesReceive Alignment/Code Errors Register Rxaligncodeerrors Receive CRC Errors Register RxcrcerrorsPause Receive Frames Register Rxpauseframes Receive Oversized Frames Register RxoversizedReceive Undersized Frames Register Rxundersized Receive Jabber Frames Register RxjabberReceive Frame Fragments Register Rxfragments Filtered Receive Frames Register RxfilteredReceive QOS Filtered Frames Register Rxqosfiltered Receive Octet Frames Register RxoctetsGood Transmit Frames Register Txgoodframes Multicast Transmit Frames Register Txmcastframes Broadcast Transmit Frames Register TxbcastframesPause Transmit Frames Register Txpauseframes Deferred Transmit Frames Register TxdeferredTransmit Single Collision Frames Register Txsinglecoll Transmit Underrun Error Register TxunderrunTransmit Multiple Collision Frames Register Txmulticoll Transmit Late Collision Frames Register TxlatecollTransmit Carrier Sense Errors Register Txcarriersense Transmit Octet Frames Register TxoctetsTransmit and Receive 64 Octet Frames Register FRAME64 Network Octet Frames Register Netoctets Receive DMA Overruns Register Rxdmaoverruns Appendix a Glossary Term Definition Table A-1. Physical Layer DefinitionsReference Additions/Modifications/Deletions Table B-1. Document Revision HistoryDSP Products Applications
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