Texas Instruments TMS320DM643X DMP manual Interrupt Control, Mdio Module Components

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Peripheral Architecture

2.6.3Interrupt Control

The EMAC control module combines multiple interrupt conditions generated by the EMAC and MDIO modules into a single interrupt signal that is mapped to a CPU interrupt via the CPU interrupt controller. The control module uses two registers to control the interrupt signal to the CPU:

∙The INTEN bit in the EMAC control module interrupt control register (EWCTL) globally enables and disables the interrupt signal to the CPU. The INTEN bit is used to drive the interrupt line low during interrupt processing so that upon reenabling the bit, the interrupt signal will rise if another interrupt condition exists; thus, creating a rising edge detectable by the CPU.

∙The EMAC control module interrupt timer count register (EWINTTCNT) is programmed with a value (EWINTTCNT) that counts down once EMAC/MDIO interrupts are enabled using EWCTL. The CPU interrupt signal is prevented from rising again until this count reaches 0.

EWINTTCNT has no effect on interrupts once the count reaches 0, so there is no induced interrupt latency on random sporadic interrupts. However, the count delays the issuance of a second interrupt immediately after a first. This protects the system from getting into an interrupt thrashing mode where the software interrupt service routine (ISR) completes processing just in time to get another interrupt. By postponing subsequent interrupts in a back-to-back condition, the software application or driver can get more work done in its ISR.

EWINTTCNT reset value can be adjusted from within the ISR according to current system load, or simply set to a fixed value that assures a maximum number of interrupts per second.

The counter counts at the peripheral clock frequency of PLL1/6; its default reset count is 0 (inactive), its maximum value is 1 FFFFh (131 071).

2.7MDIO Module

The MDIO module is used to manage up to 32 physical layer (PHY) devices connected to the Ethernet Media Access Controller (EMAC). The DM643x device supports a single PHY being connected to the EMAC at any given time. The MDIO module is designed to allow almost transparent operation of the MDIO interface with little maintenance from the CPU.

The MDIO module continuously polls 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY device has been detected, the MDIO module reads the MDIO PHY link status register (LINK) to monitor the PHY link state. Link change events are stored in the MDIO module, which can interrupt the CPU. This storing of the events allows the CPU to poll the link status of the PHY device without continuously performing MDIO module accesses. However, when the CPU must access the MDIO module for configuration and negotiation, the MDIO module performs the MDIO read or write operation independent of the CPU. This independent operation allows the processor to poll for completion or interrupt the CPU once the operation has completed.

2.7.1MDIO Module Components

The MDIO module (Figure 9) interfaces to the PHY components through two MDIO pins (MDCLK and MDIO), and to the CPU through the EMAC control module and the configuration bus. The MDIO module consists of the following logical components:

∙MDIO clock generator

∙Global PHY detection and link state monitoring

∙Active PHY monitoring

∙PHY register user access

28 Ethernet Media Access Controller (EMAC)/SPRU941A –April 2007

Management Data Input/Output (MDIO)

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Contents Users Guide Submit Documentation Feedback Contents MAC Hash Address Register 1 MACHASH1 Appendix a Appendix BList of Figures Transmit Pacing Algorithm Test Register Tpacetest List of Tables Fifo Control Register Fifocontrol Field Descriptions Read This First Features Purpose of the PeripheralFunctional Block Diagram Emac and Mdio Block DiagramSignal Descriptions Industry Standards Compliance StatementClock Control Memory MapEmac and Mdio Signals Signal Type DescriptionEthernet Protocol Overview Ethernet Frame FormatEthernet Frame Description Field Bytes DescriptionProgramming Interface Ethernet’s Multiple Access ProtocolPacket Buffer Descriptors Basic Descriptor Description Typical Descriptor Linked ListTransmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Transmit Buffer Descriptor Format Example 1. Transmit Buffer Descriptor in C Structure FormatNext Descriptor Pointer Buffer PointerBuffer Offset Buffer LengthEnd of Packet EOP Flag Ownership Owner FlagEnd of Queue EOQ Flag Teardown Complete Tdowncmplt FlagReceive Buffer Descriptor Format Receive Buffer Descriptor FormatExample 2. Receive Buffer Descriptor in C Structure Format #define Emacdscflagjabber Buffer Length Code Error Codeerror Flag Alignment Error Alignerror FlagCRC Error Crcerror Flag Jabber FlagEmac Control Module No Match Nomatch FlagInternal Memory Bus ArbiterInterrupt Control Mdio ModuleMdio Module Components PHY Register User Access Mdio Clock GeneratorGlobal PHY Detection and Link State Monitoring Active PHY MonitoringMdio Module Operational Overview Writing Data To a PHY Register Initializing the Mdio ModuleReading Data From a PHY Register Example of Mdio Register Access Code Example 3. Mdio Register Access MacrosEmac Module Emac Module ComponentsReceive DMA Engine Receive FifoClock and Reset Logic Transmit DMA EngineTransmit Fifo MAC TransmitterMedia Independent Interface MII Data ReceptionReceive Control Receive Inter-Frame IntervalCollision-Based Receive Buffer Flow Control Ieee 802.3x-Based Receive Buffer Flow ControlTransmit Control CRC InsertionAdaptive Performance Optimization APO Interpacket-Gap IPG EnforcementTransmit Flow Control Speed, Duplex, and Pause Frame SupportReceive DMA Host Configuration Packet Receive OperationReceive Channel Enabling Receive Address MatchingHost Free Buffer Tracking Hardware Receive QOS SupportReceive Channel Teardown Promiscuous Receive Mode Receive Frame ClassificationReceive Frame Treatment Summary Receive Frame TreatmentMiddle of Frame Overrun Treatment Receive OverrunMiddle of Frame Overrun Treatment Transmit DMA Host Configuration Packet Transmit OperationReceive and Transmit Latency Transmit Channel TeardownSoftware Reset Considerations Reset ConsiderationsTransfer Node Priority Hardware Reset Considerations InitializationEnabling the EMAC/MDIO Peripheral Emac Control Module InitializationMdio Module Initialization Example 4. Emac Control Module Initialization CodeExample 5. Mdio Module Initialization Code Emac Module Initialization Interrupt Support Emac Module Interrupt Events and RequestsTransmit Packet Completion Interrupts Receive Packet Completion InterruptsHost Error Interrupt Statistics InterruptUser Access Completion Interrupt Mdio Module Interrupt Events and RequestsLink Change Interrupt Proper Interrupt ProcessingEmulation Considerations Power ManagementEmulation Control Emac Control Module Interrupt Control Register Ewctl Emac Control Module RegistersAcronym Register Description Bit FieldEmac Control Module Interrupt Timer Count Register Ewinttcnt Management Data Input/Output Mdio Registers Mdio Version Register VersionMdio Version Register Version Field Descriptions Mdio Control Register Control Mdio Control Register Control Field DescriptionsPHY Acknowledge Status Register Alive PHY Link Status Register LinkPHY Acknowledge Status Register Alive Field Descriptions PHY Link Status Register Link Field DescriptionsNo Mdio link change event Will clear the event and writing a 0 has no effect No Mdio user command complete event USERINTMASKED0 and USERINTMASKED1 correspond to USERACCESS0 WS-0 Userintmaskclear Mdio User Access Register 0 USERACCESS0 Mdio User Access Register 0 USERACCESS0 Field DescriptionsMdio User PHY Select Register 0 USERPHYSEL0 Linksel LinkintenbPhyadrmon Bit Field Value DescriptionMdio User Access Register 1 USERACCESS1 Mdio User Access Register 1 USERACCESS1 Field DescriptionsMdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1Ethernet Media Access Controller Emac Registers Ethernet Media Access Controller Emac Registers Offset Acronym Register DescriptionOffset Acronym Register Description Network Statistics RegistersTransmit Control Register Txcontrol Transmit Identification and Version Register TxidverTransmit Control Register Txcontrol Field Descriptions Transmit Teardown Register Txteardown Field Descriptions Transmit Teardown Register TxteardownTxtdnch Receive Control Register Rxcontrol Receive Identification and Version Register RxidverReceive Control Register Rxcontrol Field Descriptions Receive Teardown Register Rxteardown Field Descriptions Receive Teardown Register RxteardownRxtdnch Transmit Interrupt Status Unmasked Register Txintstatraw TX7PENDTransmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register TxintstatmaskedTransmit Interrupt Mask Set Register Txintmaskset TX7MASKTransmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register TxintmaskclearMAC Input Vector Register Macinvector MAC Input Vector Register Macinvector Field DescriptionsUserint Linkint Hostpend Statpend Rxpend TxpendReceive Interrupt Status Unmasked Register Rxintstatraw RX7PENDReceive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register RxintstatmaskedReceive Interrupt Mask Set Register Rxintmaskset RX7MASKReceive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register RxintmaskclearMAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Status Unmasked Register MacintstatrawHostpend Statpend MAC Interrupt Mask Set Register Macintmaskset MAC Interrupt Mask Clear Register MacintmaskclearHostmask Statmask HostmaskRxpasscrc Rxqosen Rxnochain RxcmfenRxcsfen Rxcefen Rxcafen RxpromchFrames containing errors are filtered Receive multicast channel select Receive Unicast Enable Set Register Rxunicastset RXCH7ENReceive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register RxunicastclearReceive Buffer Offset Register Rxbufferoffset Receive Maximum Length Register RxmaxlenReceive Maximum Length Register Rxmaxlen Field Descriptions Rxfilterthresh Reserved RX nFLOWTHRESH FFhReceive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol MAC Control Register Maccontrol Field DescriptionsSent. Full-duplex mode no outgoing pause frames are sent LoopbackMAC Status Register Macstatus MAC Status Register Macstatus Field DescriptionsMAC Status Register Macstatus Field Descriptions Bit Field Value DescriptionEmulation Control Register Emcontrol Fifo Control Register FifocontrolEmulation Control Register Emcontrol Field Descriptions Fifo Control Register Fifocontrol Field DescriptionsMAC Configuration Register Macconfig Soft Reset Register SoftresetMAC Configuration Register Macconfig Field Descriptions Soft Reset Register Softreset Field DescriptionsMAC Source Address Low Bytes Register Macsrcaddrlo MAC Source Address High Bytes Register MacsrcaddrhiMAC Hash Address Register 1 MACHASH1 MAC Hash Address Register 2 MACHASH2MAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 2 MACHASH2 Field DescriptionsTransmit Pacing Algorithm Test Register Tpacetest Back Off Test Register BofftestBack Off Test Register Bofftest Field Descriptions Receive Pause Timer Register Rxpause Transmit Pause Timer Register TxpauseReceive Pause Timer Register Rxpause Field Descriptions Transmit Pause Timer Register Txpause Field DescriptionsMAC Address High Bytes Register Macaddrhi MAC Address Low Bytes Register MacaddrloMAC Address Low Bytes Register Macaddrlo Field Descriptions MAC Index Register Macindex Field Descriptions MAC Index Register MacindexMacindex TX nHDP Transmit Channel 0-7 Completion Pointer Register TXnCP Receive Channel 0-7 Completion Pointer Register RXnCPNetwork Statistics Registers Good Receive Frames Register RxgoodframesBroadcast Receive Frames Register Rxbcastframes Multicast Receive Frames Register RxmcastframesReceive CRC Errors Register Rxcrcerrors Receive Alignment/Code Errors Register RxaligncodeerrorsPause Receive Frames Register Rxpauseframes Receive Oversized Frames Register RxoversizedReceive Jabber Frames Register Rxjabber Receive Undersized Frames Register RxundersizedReceive Frame Fragments Register Rxfragments Filtered Receive Frames Register RxfilteredReceive Octet Frames Register Rxoctets Receive QOS Filtered Frames Register RxqosfilteredGood Transmit Frames Register Txgoodframes Broadcast Transmit Frames Register Txbcastframes Multicast Transmit Frames Register TxmcastframesPause Transmit Frames Register Txpauseframes Deferred Transmit Frames Register TxdeferredTransmit Underrun Error Register Txunderrun Transmit Single Collision Frames Register TxsinglecollTransmit Multiple Collision Frames Register Txmulticoll Transmit Late Collision Frames Register TxlatecollTransmit Octet Frames Register Txoctets Transmit Carrier Sense Errors Register TxcarriersenseTransmit and Receive 64 Octet Frames Register FRAME64 Network Octet Frames Register Netoctets Receive DMA Overruns Register Rxdmaoverruns Appendix a Glossary Table A-1. Physical Layer Definitions Term DefinitionTable B-1. Document Revision History Reference Additions/Modifications/DeletionsProducts Applications DSP
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