Analog Devices ADSP-2181 manual ADSP-2183-SPECIFICATIONS

Page 16

ADSP-2181/ADSP-2183

ADSP-2183–SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

 

 

 

K Grade

 

B Grade

 

Parameter

 

Min

Max

Min

Max

Unit

 

 

 

 

 

 

 

VDD

Supply Voltage

3.0

3.6

3.0

3.6

V

TAMB

Ambient Operating Temperature

0

+70

–40

+85

°C

ELECTRICAL CHARACTERISTICS

 

 

 

 

K/B Grades

 

Parameter

 

Test Conditions

Min

Max

Unit

 

 

 

 

 

 

VIH

Hi-Level Input Voltage1, 2

@ VDD = max

2.0

 

V

VIH

Hi-Level CLKIN Voltage

@ VDD = max

2.2

 

V

VIL

Lo-Level Input Voltage1, 3

@ VDD = min

 

0.4

V

VOH

Hi-Level Output Voltage1, 4, 5

@ VDD = min

 

 

 

 

 

IOH = –0.5 mA

2.4

 

V

 

 

@ VDD = min

 

 

 

VOL

Lo-Level Output Voltage1, 4, 5

IOH = –100 μA6

VDD – 0.3

V

@ VDD = min

 

 

 

IIH

Hi-Level Input Current3

IOL = 2 mA

 

0.4

V

@ VDD = max

 

 

μA

IIL

Lo-Level Input Current3

VIN = VDD max

 

10

@ VDD = max

 

 

μA

IOZH

Three-State Leakage Current7

VIN = 0 V

 

10

@ VDD = max,

 

 

μA

IOZL

Three-State Leakage Current7

VIN = VDD max8

 

10

@ VDD = max,

 

 

μA

IDD

Supply Current (Idle)9, 10

VIN = 0 V8

 

10

@ VDD = max, tCK = 34.7 ns

 

9

mA

IDD

Supply Current (Dynamic)10, 11

@ VDD = max

 

 

 

CI

Input Pin Capacitance3, 6, 13

tCK = 34.7 ns12

 

54

mA

@ VIN = 2.5 V,

 

 

 

 

 

fIN = 1.0 MHz,

 

 

 

CO

Output Pin Capacitance6, 7, 13, 14

TAMB = +25°C

 

8

pF

@ VIN = 2.5 V,

 

 

 

 

 

fIN = 1.0 MHz,

 

 

 

 

 

TAMB = +25°C

 

8

pF

NOTES

1Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, IAD0–IAD15, PF0–PF7.

2Input only pins: RESET, IRQ2, BR, MMAP, DR0, DR1, PWD, IRQL0, IRQL1, IRQE, IS, IRD, IWR, IAL.

3Input only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR0, DR1, IS, IAL, IRD, IWR, IRQL0, IRQL1, IRQE, PWD.

4Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, IACK, PWDACK, A0-A13, DT0, DT1, CLKOUT, FL2-0.

5Although specified for TTL outputs, all ADSP-2183 outputs are CMOS-compatible and will drive to V DD and GND, assuming no dc loads. 6Guaranteed but not tested.

7Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RSF1, IAD0–IAD15, PF0–PF7.

80 V on BR, CLKIN Active (to force three-state condition).

9Idle refers to ADSP-2183 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND.

10Current reflects device operating with no output loads.

11IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2 and type 6, and 20% are idle instructions.

12VIN = 0.4 V and 2.4 V. For typical figures for supply currents, refer to “Power Dissipation” section.

13Applies to TQFP and PQFP package types.

14Output pin capacitance is the capacitive load for any three-stated output pin.

Specifications subject to change without notice.

–16–

REV. 0

Image 16
Contents Functional Block Diagram General DescriptionADSP-2181/ADSP-2183 Architecture OverviewADSP-2181/ADSP-2183 Integration Pin Input Names Pins Output Function PIN DescriptionsInterrupt Vector Source of Interrupt Address HexHighest Priority Lowest PrioritySystem Interface ADSP-2181 ADSP-2183Pmovlay Memory A13 A120Internal Address Range Wait State RegisterMemory Space Word Size Alignment Booting Method Idma Port BootingSyntax IOaddr = dreg dreg = IOaddr Biased RoundingInstruction SET Description Designing AN EZ-ICE-COMPATIBLE SystemReset GND PM, DM, BM, IOM, & CMGrade Parameter Min Max Unit Grades Parameter Test Conditions Min Max UnitMemory Timing Specifications Frequency Dependency for Timing SpecificationsAbsolute Maximum Ratings ESD Sensitivity50C/W 2C/W 48C/W Package41C/W 10C/W 31C/W Capacitive Loading Test ConditionsADSP-2183-SPECIFICATIONS ADSP-2183 Timing Parameters Tqfp Delay Valid Output Control Signals Parameter Min Max Unit Clock Signals and Reset28.8 MHz Parameter Min Max Clock Signals and Reset FI, or PFx Setup before Clkout Low1, 2, 3 25tCK + IRQx Flag Output Delay from Clkout Low5 25tCK +Parameter Min Max Unit Interrupts and Flag Flag Output Hold after Clkout Low5 5tCKParameter Min Max Unit Bus Request/Grant Parameter Min Max Unit Memory Read 28.8 MHz Parameter Min Max Unit Memory ReadParameter Min Max Unit Memory Write Parameter Min Max Unit Serial Ports Parameter Min Max Unit Idma Address Latch 28.8 MHz Parameter Min Max Unit Idma Write, Short Write CycleParameter Min Max Idma Write, Short Write Cycle Parameter Min Max Unit Idma Write, Long Write Cycle Parameter Min Max Unit Idma Read, Long Read Cycle 28.8 MHz Parameter Min Max Unit Idma Read, Long Read CycleParameter Min Max Unit Idma Read, Short Read Cycle 28.8 MHz Parameter Min Max Unit Idma Read, Short Read CycleLead Tqfp Package Pinout Pin Number NameMillimeters Inches Symbol MIN TYP MAX Outline DimensionsLead Pqfp Package Pinout PF0 160 Ordering Guide Page Page C2144-16-6/96