Analog Devices ADSP-2181 manual Parameter Min Max Unit Idma Write, Short Write Cycle, 28.8 MHz

Page 27

ADSP-2181/ADSP-2183

ADSP-2181

Parameter					Min	Max	Unit

IDMA Write, Short Write Cycle
Timing Requirements:
tIKW	IACK	Low before Start of Write1			0		ns
tIWP	Duration of Write1, 2				15		ns
tIDSU	IAD15–0 Data Setup before End of Write2, 3, 4				5		ns
tIDH	IAD15–0 Data Hold after End of Write2, 3, 4				2		ns
Switching Characteristics:
tIKHW	Start of Write to		IACK	High		15	ns

ADSP-2183

						28.8 MHz
Parameter					Min	Max
IDMA Write, Short Write Cycle
Timing Requirements:
tIKW	IACK	Low before Start of Write1			0
tIWP	Duration of Write1, 2				15
tIDSU	IAD15–0 Data Setup before End of Write2, 3, 4				5
tIDH	IAD15–0 Data Hold after End of Write2, 3, 4				2
Switching Characteristics:
tIKHW	Start of Write to		IACK	High		17

NOTES

1Start of Write = IS Low and IWR Low.

2End of Write = IS High or IWR High.

3If Write Pulse ends before IACK Low, use specifications tIDSU, tIDH. 4If Write Pulse ends after IACK Low, use specifications tIKSU, tIKH.

	tIKW
IACK
	tIKHW
IS
	tIWP
IWR
	tIDH
	tIDSU
IAD 15–0	DATA

Unit

ns ns ns ns

ns

Figure 29. IDMA Write, Short Write Cycle

REV. 0

–27–

Image 27

Contents General Description Functional Block DiagramArchitecture Overview ADSP-2181/ADSP-2183ADSP-2181/ADSP-2183 Integration PIN Descriptions Pin Input Names Pins Output FunctionLowest Priority Interrupt VectorSource of Interrupt Address Hex Highest PriorityADSP-2181 ADSP-2183 System InterfaceMemory A13 A120 PmovlayAddress Range Wait State Register InternalMemory Space Word Size Alignment Idma Port Booting Booting MethodDesigning AN EZ-ICE-COMPATIBLE System Syntax IOaddr = dreg dreg = IOaddrBiased Rounding Instruction SET DescriptionPM, DM, BM, IOM, & CM Reset GNDGrades Parameter Test Conditions Min Max Unit Grade Parameter Min Max UnitESD Sensitivity Memory Timing SpecificationsFrequency Dependency for Timing Specifications Absolute Maximum RatingsPackage 50C/W 2C/W 48C/W41C/W 10C/W 31C/W Test Conditions Capacitive LoadingADSP-2183-SPECIFICATIONS ADSP-2183 Timing Parameters Tqfp Delay Valid Output Parameter Min Max Unit Clock Signals and Reset Control Signals28.8 MHz Parameter Min Max Clock Signals and Reset Flag Output Hold after Clkout Low5 5tCK FI, or PFx Setup before Clkout Low1, 2, 3 25tCK + IRQxFlag Output Delay from Clkout Low5 25tCK + Parameter Min Max Unit Interrupts and FlagParameter Min Max Unit Bus Request/Grant 28.8 MHz Parameter Min Max Unit Memory Read Parameter Min Max Unit Memory ReadParameter Min Max Unit Memory Write Parameter Min Max Unit Serial Ports Parameter Min Max Unit Idma Address Latch Parameter Min Max Unit Idma Write, Short Write Cycle 28.8 MHzParameter Min Max Idma Write, Short Write Cycle Parameter Min Max Unit Idma Write, Long Write Cycle 28.8 MHz Parameter Min Max Unit Idma Read, Long Read Cycle Parameter Min Max Unit Idma Read, Long Read Cycle28.8 MHz Parameter Min Max Unit Idma Read, Short Read Cycle Parameter Min Max Unit Idma Read, Short Read CycleLead Tqfp Package Pinout Number Name PinOutline Dimensions Millimeters Inches Symbol MIN TYP MAXLead Pqfp Package Pinout PF0 160 Ordering Guide Page Page C2144-16-6/96