Analog Devices ADSP-2181, ADSP-2183 manual Delay Valid Output

Page 19

ADSP-2181/ADSP-2183

ADSP-2183

CAPACITIVE LOADING

Figures 17 and 18 show the capacitive loading characteristics of the ADSP-2183.

 

30

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T = +85°C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDD = 3.0V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

– ns

25

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

– 2.4V)

20

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(0.4VTIME

15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RISE

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

25

50

75

100

125

150

175

200

 

0

CL – pF

Figure 17. Typical Output Rise Time vs. Load Capacitance, CL (at Maximum Ambient Operating Temperature)

18

16

14

from which

tDIS = tMEASURED – tDECAY

is calculated. If multiple pins (such as the data bus) are dis- abled, the measurement value is that of the last pin to stop driving.

3.0V

INPUT1.5V 0.0V

2.0V

OUTPUT1.5V 0.3V

Figure 19. Voltage Reference Levels for AC Measure- ments (Except Output Enable/Disable)

Output Enable Time

Output pins are considered to be enabled when that have made a transition from a high-impedance state to when they start driving. The output enable time (tENA) is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the Output Enable/Disable diagram. If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving.

DELAY

 

12

ns

10

 

VALID OUTPUT

OR HOLD –

8

6

4

2

NOMINAL

–2

–4

–6

REFERENCE

SIGNAL

tMEASURED

VOH tDIS

(MEASURED)

VOH (MEASURED) – 0.5V

OUTPUT

VOL (MEASURED) +0.5V

VOL

 

 

 

tDECAY

(MEASURED)

 

 

 

OUTPUT STOPS

DRIVING

tENA

VOH

(MEASURED)

2.0V

1.0V

VOL

(MEASURED)

OUTPUT STARTS

DRIVING

0

25

50

75

100

125

150

175

200

 

 

 

 

CL – pF

 

 

 

 

HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.

Figure 18. Typical Output Valid Delay or Hold vs. Load Capacitance, CL (at Maximum Ambient Operating Temperature)

TEST CONDITIONS

Output Disable Time

Output pins are considered to be disabled when they have stopped driving and started a transition from the measured out- put high or low voltage to a high impedance state. The output

disable time (tDIS) is the difference of tMEASURED and tDECAY, as shown in the Output Enable/Disable diagram. The time is the

interval from when a reference signal reaches a high or low volt- age level to when the output voltages have changed by 0.5 V from the measured output high or low voltage. The decay time,

tDECAY, is dependent on the capacitive load, CL, and the current load, iL, on the output pin. It can be approximated by the fol-

lowing equation:

tDECAY = CL •i0.5V L

Figure 20. Output Enable/Disable

IOL

TO

OUTPUT +1.5V PIN

50pF

IOH

Figure 21. Equivalent Device Loading for AC Measure- ments (Including All Fixtures)

REV. 0

–19–

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Contents General Description Functional Block DiagramArchitecture Overview ADSP-2181/ADSP-2183ADSP-2181/ADSP-2183 Integration PIN Descriptions Pin Input Names Pins Output FunctionLowest Priority Interrupt VectorSource of Interrupt Address Hex Highest PriorityADSP-2181 ADSP-2183 System InterfaceMemory A13 A120 PmovlayInternal Address Range Wait State RegisterMemory Space Word Size Alignment Idma Port Booting Booting MethodDesigning AN EZ-ICE-COMPATIBLE System Syntax IOaddr = dreg dreg = IOaddrBiased Rounding Instruction SET DescriptionPM, DM, BM, IOM, & CM Reset GNDGrades Parameter Test Conditions Min Max Unit Grade Parameter Min Max UnitESD Sensitivity Memory Timing SpecificationsFrequency Dependency for Timing Specifications Absolute Maximum Ratings50C/W 2C/W 48C/W Package41C/W 10C/W 31C/W Test Conditions Capacitive LoadingADSP-2183-SPECIFICATIONS ADSP-2183 Timing Parameters Tqfp Delay Valid Output Control Signals Parameter Min Max Unit Clock Signals and Reset28.8 MHz Parameter Min Max Clock Signals and Reset Flag Output Hold after Clkout Low5 5tCK FI, or PFx Setup before Clkout Low1, 2, 3 25tCK + IRQxFlag Output Delay from Clkout Low5 25tCK + Parameter Min Max Unit Interrupts and FlagParameter Min Max Unit Bus Request/Grant 28.8 MHz Parameter Min Max Unit Memory Read Parameter Min Max Unit Memory ReadParameter Min Max Unit Memory Write Parameter Min Max Unit Serial Ports Parameter Min Max Unit Idma Address Latch 28.8 MHz Parameter Min Max Unit Idma Write, Short Write CycleParameter Min Max Idma Write, Short Write Cycle Parameter Min Max Unit Idma Write, Long Write Cycle 28.8 MHz Parameter Min Max Unit Idma Read, Long Read Cycle Parameter Min Max Unit Idma Read, Long Read Cycle28.8 MHz Parameter Min Max Unit Idma Read, Short Read Cycle Parameter Min Max Unit Idma Read, Short Read CycleLead Tqfp Package Pinout Number Name PinOutline Dimensions Millimeters Inches Symbol MIN TYP MAXLead Pqfp Package Pinout PF0 160 Ordering Guide Page Page C2144-16-6/96
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