Analog Devices ADSP-2183, ADSP-2181 manual Package, 50C/W 2C/W 48C/W, 41C/W 10C/W 31C/W

Page 14

ADSP-2181/ADSP-2183

ADSP-2181

ENVIRONMENTAL CONDITIONS

Ambient Temperature Rating:

TAMB = TCASE – (PD × θCA)

TCASE = Case Temperature in °C PD = Power Dissipation in W

θCA = Thermal Resistance (Case-to-Ambient)

θJA = Thermal Resistance (Junction-to-Ambient)

θJC = Thermal Resistance (Junction-to-Case)

Package

θJA

θJC

 

θCA

 

 

 

 

 

 

 

 

TQFP

50°C/W

2°C/W

 

48°C/W

PQFP

41°C/W

10°C/W

 

31°C/W

 

 

 

 

 

 

 

 

 

 

1000

 

 

 

 

 

 

VDD = 5.5V

 

 

 

 

 

 

 

 

µA

 

 

 

 

 

 

 

VDD = 5.0V

 

 

 

 

 

 

 

VDD = 4.5V

 

 

 

 

 

 

 

 

(LOG SCALE)

100

 

 

 

 

 

 

 

CURRENT

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

25

55

85

 

–5

TEMPERATURE – °C

NOTES:

1.REFLECTS ADSP-2181 OPERATION IN LOWEST POWER MODE. (SEE "SYSTEM INTERFACE" CHAPTER OF THE ADSP-2100 FAMILY USER'S MANUAL FOR DETAILS.)

2.CURRENT REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.

Figure 8. Power-Down Supply Current (Typical)

POWER DISSIPATION

To determine total power dissipation in a specific application, the following equation should be applied for each output:

C × VDD2 × f

C = load capacitance, f = output switching frequency.

Example:

In an application where external data memory is used and no other outputs are active, power dissipation is calculated as follows:

Assumptions:

External data memory is accessed every cycle with 50% of the address pins switching.

External data memory writes occur every other cycle with 50% of the data pins switching.

Each address and data pin has a 10 pF total load at the pin.

The application operates at VDD = 5.0 V and tCK = 30 ns.

Total Power Dissipation = PINT + (C × VDD2 × f )

PINT = internal power dissipation from Power vs. Frequency graph (Figure 9).

(C × VDD2 × f ) is calculated for each output:

 

 

 

 

 

 

# of

 

 

 

 

 

 

 

 

 

 

 

 

 

Pins

× C

× VDD2

× f

 

 

 

Address,

 

 

 

 

8

× 10 pF

× 52

V

× 33.3 MHz

=

66.6 mW

DMS

Data Output,

 

 

9

× 10 pF

× 52

V

× 16.67 MHz

=

37.5 mW

WR

RD

 

1

× 10 pF

× 52

V

× 16.67 MHz

=

4.2 mW

CLKOUT

1

× 10 pF

× 52

V

× 33.3 MHz

=

8.3 mW

 

 

 

 

 

 

 

 

 

 

 

 

116.6 mW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Total power dissipation for this example is PINT + 116.6 mW.

 

570

2181 POWER, INTERNAL

 

 

 

 

 

 

 

 

 

550

 

 

VDD = 5.5V

 

 

 

 

530

 

 

 

550mW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

mW

510

490mW

 

 

 

 

 

480

 

 

 

 

 

 

) –

450

 

 

 

 

 

 

INT

 

 

 

 

 

 

420

 

 

VDD = 5.0V

 

 

 

(P

 

 

 

 

 

POWER

390

365mW

 

 

 

425mW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

360

 

 

 

 

 

 

 

330

 

 

VDD = 4.5V

 

 

 

 

300

275mW

 

 

 

330mW

 

 

270

 

 

 

 

 

 

 

240

29

30

31

32

33

 

 

28

34

 

 

 

 

1/tCK – MHz

 

 

 

POWER, IDLE1, 2

 

95

 

 

 

 

 

 

 

90

 

VDD = 5.5V

 

 

 

 

85

 

 

90mW

 

 

 

 

 

 

 

 

– mW

80

 

 

 

 

 

 

75

 

 

 

 

 

 

)

 

75mW

 

 

 

 

 

IDLE

70

VDD

= 5.0V

 

 

 

 

 

 

 

(P

65

 

 

 

 

70mW

 

POWER

 

 

 

 

 

 

60

60mW

 

 

 

 

 

55

VDD = 4.5V

 

 

 

 

 

 

 

 

50

 

 

 

 

54mW

 

 

45

47mW

 

 

 

 

 

 

 

 

 

 

 

 

 

40

 

 

 

 

 

 

 

28

29

30

31

32

33

34

 

 

 

1/fCK – MHz

 

 

 

 

75

 

 

 

POWER, IDLE n MODES3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

70

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IDLE;

 

65

 

 

 

 

 

 

 

 

 

 

 

70mW

 

 

mW

60

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

60mW

 

 

 

 

 

 

 

 

 

 

 

)

55

 

 

 

 

 

 

 

 

 

 

 

 

n

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IDLE

50

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(P

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

POWER

45

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

40

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

35mW

 

IDLE (16)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

35

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31mW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IDLE (128)

 

30

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

33mW

 

 

 

25

 

 

29mW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

28

29

30

31

32

33

34

1/fCK – MHz

VALID FOR ALL TEMPERATURE GRADES.

1POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.

2IDLE REFERS TO ADSP-2181 STATE OF OPERATION DURING EXECUTION OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER VDD OR GND.

3TYPICAL POWER DISSIPATION AT 5.0V VDD DURING EXECUTION OF IDLE n

INSTRUCTION (CLOCK FREQUENCY REDUCTION).

4IDD MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1,4,5,12,13,14), 30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS.

Figure 9. Power vs. Frequency

–14–

REV. 0

Image 14
Contents Functional Block Diagram General DescriptionADSP-2181/ADSP-2183 Architecture OverviewADSP-2181/ADSP-2183 Integration Pin Input Names Pins Output Function PIN DescriptionsHighest Priority Interrupt VectorSource of Interrupt Address Hex Lowest PrioritySystem Interface ADSP-2181 ADSP-2183Pmovlay Memory A13 A120Memory Space Word Size Alignment Address Range Wait State RegisterInternal Booting Method Idma Port BootingInstruction SET Description Syntax IOaddr = dreg dreg = IOaddrBiased Rounding Designing AN EZ-ICE-COMPATIBLE SystemReset GND PM, DM, BM, IOM, & CMGrade Parameter Min Max Unit Grades Parameter Test Conditions Min Max UnitAbsolute Maximum Ratings Memory Timing SpecificationsFrequency Dependency for Timing Specifications ESD Sensitivity41C/W 10C/W 31C/W Package50C/W 2C/W 48C/W Capacitive Loading Test ConditionsADSP-2183-SPECIFICATIONS ADSP-2183 Timing Parameters Tqfp Delay Valid Output 28.8 MHz Parameter Min Max Clock Signals and Reset Parameter Min Max Unit Clock Signals and ResetControl Signals Parameter Min Max Unit Interrupts and Flag FI, or PFx Setup before Clkout Low1, 2, 3 25tCK + IRQxFlag Output Delay from Clkout Low5 25tCK + Flag Output Hold after Clkout Low5 5tCKParameter Min Max Unit Bus Request/Grant Parameter Min Max Unit Memory Read 28.8 MHz Parameter Min Max Unit Memory ReadParameter Min Max Unit Memory Write Parameter Min Max Unit Serial Ports Parameter Min Max Unit Idma Address Latch Parameter Min Max Idma Write, Short Write Cycle Parameter Min Max Unit Idma Write, Short Write Cycle28.8 MHz Parameter Min Max Unit Idma Write, Long Write Cycle Parameter Min Max Unit Idma Read, Long Read Cycle 28.8 MHz Parameter Min Max Unit Idma Read, Long Read CycleParameter Min Max Unit Idma Read, Short Read Cycle 28.8 MHz Parameter Min Max Unit Idma Read, Short Read CycleLead Tqfp Package Pinout Pin Number NameMillimeters Inches Symbol MIN TYP MAX Outline DimensionsLead Pqfp Package Pinout PF0 160 Ordering Guide Page Page C2144-16-6/96