Analog Devices ADSP-2181 manual ADSP-2183 Timing Parameters

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ADSP-2181/ADSP-2183

ADSP-2183

ABSOLUTE MAXIMUM RATINGS*

 

 

Supply Voltage

. . . . –0.3 V to +4.6

V

Input Voltage

–0.5 V to VDD + 0.5

V

Output Voltage Swing

–0.5 V to VDD + 0.5

V

Operating Temperature Range (Ambient)

. . . . –40°C to +85°C

Storage Temperature Range

. . . . –65°C to +150°C

Lead Temperature (5 sec) TQFP

. . . . . . . . . . . +280°C

*Stresses above those listed under “Absolute Maximum Ratings” may cause perma- nent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD SENSITIVITY

The ADSP-2183 is an ESD (electrostatic discharge) sensitive device. Electrostatic charges readily accumulate on the human body and equipment and can discharge without detection. Permanent damage may occur to devices subjected to high energy electrostatic discharges.

The ADSP-2183 features proprietary ESD protection circuitry to dissipate high energy discharges (Human Body Model). Per method 3015 of MIL-STD-883, the ADSP-2183 has been classified as a Class 2 device.

Proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Unused devices must be stored in conductive foam or shunts, and the foam should be discharged to the destination before devices are removed.

WARNING!

ESD SENSITIVE DEVICE

ADSP-2183 TIMING PARAMETERS

GENERAL NOTES

Use the exact timing information given. Do not attempt to de- rive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, you cannot meaningfully add up parameters to derive longer times.

TIMING NOTES

Switching characteristics specify how the processor changes its sig- nals. You have no control over this timing—circuitry external to the processor must be designed for compatibility with these sig- nal characteristics. Switching characteristics tell you what the processor will do in a given circumstance. You can also use switch- ing characteristics to ensure that any timing requirement of a de- vice connected to the processor (such as memory) is satisfied.

Timing requirements apply to signals that are controlled by cir- cuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices.

MEMORY TIMING SPECIFICATIONS

The table below shows common memory device specifications and the corresponding ADSP-2183 timing parameters, for your convenience.

Memory

ADSP-2183

 

Timing

Device

Timing

 

Parameter

Specification

Parameter

 

Definition

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address Setup to

tASW

 

A0–A13,

 

 

 

Setup before

xMS

Write Start

 

 

WR

Low

Address Setup to

tAW

 

A0–A13,

xMS

Setup before

Write End

 

 

WR Deasserted

Address Hold Time

tWRA

 

A0–A13,

xMS

Hold after

 

 

 

WR

Deasserted

Data Setup Time

tDW

 

Data Setup before

WR

 

 

 

 

High

Data Hold Time

tDH

 

Data Hold after

WR

High

OE to Data Valid

tRDD

 

RD Low to Data Valid

Address Access Time

tAA

 

A0–A13,

xMS

to Data Valid

xMS = PMS, DMS, BMS, CMS, IOMS

FREQUENCY DEPENDENCY FOR TIMING

SPECIFICATIONS

tCK is defined as 0.5tCKI. The ADSP-2183 uses an input clock with a frequency equal to half the instruction rate: a 14.4 MHz input clock (which is equivalent to 57.6 ns) yields a 34.7 ns pro- cessor cycle (equivalent to 28.8 MHz). tCK values within the range of 0.5tCKI period should be substituted for all relevant timing parameters to obtain the specification value.

Example: tCKH = 0.5tCK – 7 ns = 0.5 (34.7 ns) – 7 ns = 11.7 ns

REV. 0

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Contents General Description Functional Block DiagramArchitecture Overview ADSP-2181/ADSP-2183ADSP-2181/ADSP-2183 Integration PIN Descriptions Pin Input Names Pins Output FunctionSource of Interrupt Address Hex Interrupt VectorHighest Priority Lowest PriorityADSP-2181 ADSP-2183 System InterfaceMemory A13 A120 PmovlayMemory Space Word Size Alignment Address Range Wait State RegisterInternal Idma Port Booting Booting MethodBiased Rounding Syntax IOaddr = dreg dreg = IOaddrInstruction SET Description Designing AN EZ-ICE-COMPATIBLE SystemPM, DM, BM, IOM, & CM Reset GNDGrades Parameter Test Conditions Min Max Unit Grade Parameter Min Max UnitFrequency Dependency for Timing Specifications Memory Timing SpecificationsAbsolute Maximum Ratings ESD Sensitivity 41C/W 10C/W 31C/W Package 50C/W 2C/W 48C/W Test Conditions Capacitive LoadingADSP-2183-SPECIFICATIONS ADSP-2183 Timing Parameters Tqfp Delay Valid Output 28.8 MHz Parameter Min Max Clock Signals and Reset Parameter Min Max Unit Clock Signals and ResetControl Signals Flag Output Delay from Clkout Low5 25tCK + FI, or PFx Setup before Clkout Low1, 2, 3 25tCK + IRQxParameter Min Max Unit Interrupts and Flag Flag Output Hold after Clkout Low5 5tCKParameter Min Max Unit Bus Request/Grant 28.8 MHz Parameter Min Max Unit Memory Read Parameter Min Max Unit Memory ReadParameter Min Max Unit Memory Write Parameter Min Max Unit Serial Ports Parameter Min Max Unit Idma Address Latch Parameter Min Max Idma Write, Short Write Cycle Parameter Min Max Unit Idma Write, Short Write Cycle28.8 MHz Parameter Min Max Unit Idma Write, Long Write Cycle 28.8 MHz Parameter Min Max Unit Idma Read, Long Read Cycle Parameter Min Max Unit Idma Read, Long Read Cycle28.8 MHz Parameter Min Max Unit Idma Read, Short Read Cycle Parameter Min Max Unit Idma Read, Short Read CycleLead Tqfp Package Pinout Number Name PinOutline Dimensions Millimeters Inches Symbol MIN TYP MAXLead Pqfp Package Pinout PF0 160 Ordering Guide Page Page C2144-16-6/96
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