Analog Devices manual ADSP-2181/ADSP-2183 Integration

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ADSP-2181/ADSP-2183

Program memory can store both instructions and data, permit- ting the ADSP-2181/ADSP-2183 to fetch two operands in a single cycle, one from program memory and one from data memory. The ADSP-2181/ADSP-2183 can fetch an operand from program memory and the next instruction in the same cycle.

In addition to the address and data bus for external memory connection, the ADSP-2181/ADSP-2183 has a 16-bit Internal DMA port (IDMA port) for connection to external systems. The IDMA port is made up of 16 data/address pins and five control pins. The IDMA port provides transparent, direct access to the DSPs on-chip program and data RAM.

An interface to low cost byte-wide memory is provided by the Byte DMA port (BDMA port). The BDMA port is bidirectional and can directly address up to four megabytes of external RAM or ROM for off-chip storage of program overlays or data tables.

The byte memory and I/O memory space interface supports slow memories and I/O memory-mapped peripherals with program- mable wait state generation. External devices can gain control of external buses with bus request/grant signals (BR, BGH, and BG). One execution mode (Go Mode) allows the ADSP-2181/ADSP- 2183 to continue running from on-chip memory. Normal execu- tion mode requires the processor to halt while buses are granted.

The ADSP-2181/ADSP-2183 can respond to eleven interrupts. There can be up to six external interrupts (one edge-sensitive, two level-sensitive, and three configurable) and seven internal interrupts generated by the timer, the serial ports (SPORTs), the Byte DMA port, and the power-down circuitry. There is also a master RESET signal.

The two serial ports provide a complete synchronous serial inter- face with optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of operation.

Each port can generate an internal programmable serial clock or accept an external serial clock.

The ADSP-2181/ADSP-2183 provides up to 13 general-purpose flag pins. The data input and output pins on SPORT1 can be alternatively configured as an input flag and an output flag. In addition, there are eight flags that are programmable as inputs or outputs, and three flags that are always outputs.

A programmable interval timer generates periodic interrupts. A 16-bit count register (TCOUNT) is decremented every n pro- cessor cycles, where n is a scaling value stored in an 8-bit regis- ter (TSCALE). When the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (TPERIOD).

Serial Ports

The ADSP-2181/ADSP-2183 incorporates two complete syn- chronous serial ports (SPORT0 and SPORT1) for serial com- munications and multiprocessor communication.

Here is a brief list of the capabilities of the ADSP-2181/ADSP- 2183 SPORTs. Refer to the ADSP-2100 Family User’s Manual for further details.

•SPORTs are bidirectional and have a separate, double- buffered transmit and receive section.

•SPORTs can use an external serial clock or generate their own serial clock internally.

•SPORTs have independent framing for the receive and trans- mit sections. Sections run in a frameless mode or with frame synchronization signals internally or externally generated.

Frame sync signals are active high or inverted, with either of two pulse widths and timings.

21xx CORE

ADSP-2181/ADSP-2183 INTEGRATION

 

 

 

 

 

 

POWER

 

2

 

 

 

 

 

 

DOWN

 

 

 

 

 

 

 

 

 

CONTROL

 

 

 

 

 

 

 

 

LOGIC

 

 

 

 

 

INSTRUCTION

PROGRAM

DATA

 

 

 

 

 

 

 

REGISTER

SRAM

SRAM

 

PROGRAMMABLE

8

 

 

 

16k × 24

16k × 16

BYTE

 

 

 

 

 

 

DMA

I/O

 

 

 

DATA

DATA

 

 

 

CONTROLLER

 

 

 

3

 

 

 

 

 

 

 

ADDRESS

ADDRESS

PROGRAM

 

 

 

 

 

 

 

 

 

FLAGS

 

 

GENERATOR

GENERATOR

 

 

 

 

 

SEQUENCER

 

 

 

 

 

#1

#2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PMA BUS

14

 

 

 

PMA BUS

 

 

 

 

 

 

 

 

 

 

 

14

 

DMA BUS

14

 

 

 

DMA BUS

MUX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EXTERNAL

 

 

 

 

 

 

 

 

ADDRESS

 

 

 

 

 

 

 

 

 

BUS

 

PMD BUS

24

 

 

 

PMD BUS

 

 

 

 

 

 

 

 

 

 

 

EXTERNAL

 

 

 

 

 

 

 

 

DATA

 

 

BUS

 

 

 

 

MUX

 

BUS

 

 

 

 

 

 

 

 

 

 

EXCHANGE

 

 

 

DMD

 

 

 

DMD BUS

 

 

 

 

 

24

 

 

 

 

 

BUS

 

 

 

 

 

 

 

 

 

 

 

 

16

 

 

 

 

 

 

 

INPUT REGS

INPUT REGS

INPUT REGS

 

COMPANDING

 

 

INTERNAL

16

 

 

 

 

CIRCUITRY

 

 

 

 

 

 

 

 

 

DMA

 

ALU

MAC

SHIFTER

 

 

 

 

 

 

 

TIMER

 

PORT

 

 

 

 

 

 

 

 

 

 

 

 

 

TRANSMIT REG

 

TRANSMIT REG

 

 

 

 

OUTPUT REGS

OUTPUT REGS

OUTPUT REGS

RECEIVE REG5

 

RECEIVE REG

 

 

 

 

 

 

 

 

 

 

 

 

 

16

 

SERIAL

 

SERIAL

 

 

 

4

 

 

 

 

 

 

 

 

 

PORT 0

 

PORT 0

INTERRUPTS

 

 

 

 

 

 

 

 

 

 

R BUS

5

 

5

 

 

 

 

 

 

 

 

 

 

 

 

Figure 1. ADSP-2181/ADSP-2183 Block Diagram

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Contents General Description Functional Block DiagramArchitecture Overview ADSP-2181/ADSP-2183ADSP-2181/ADSP-2183 Integration PIN Descriptions Pin Input Names Pins Output FunctionLowest Priority Interrupt VectorSource of Interrupt Address Hex Highest PriorityADSP-2181 ADSP-2183 System InterfaceMemory A13 A120 PmovlayAddress Range Wait State Register InternalMemory Space Word Size Alignment Idma Port Booting Booting MethodDesigning AN EZ-ICE-COMPATIBLE System Syntax IOaddr = dreg dreg = IOaddrBiased Rounding Instruction SET DescriptionPM, DM, BM, IOM, & CM Reset GNDGrades Parameter Test Conditions Min Max Unit Grade Parameter Min Max UnitESD Sensitivity Memory Timing SpecificationsFrequency Dependency for Timing Specifications Absolute Maximum RatingsPackage 50C/W 2C/W 48C/W41C/W 10C/W 31C/W Test Conditions Capacitive LoadingADSP-2183-SPECIFICATIONS ADSP-2183 Timing Parameters Tqfp Delay Valid Output Parameter Min Max Unit Clock Signals and Reset Control Signals28.8 MHz Parameter Min Max Clock Signals and Reset Flag Output Hold after Clkout Low5 5tCK FI, or PFx Setup before Clkout Low1, 2, 3 25tCK + IRQxFlag Output Delay from Clkout Low5 25tCK + Parameter Min Max Unit Interrupts and FlagParameter Min Max Unit Bus Request/Grant 28.8 MHz Parameter Min Max Unit Memory Read Parameter Min Max Unit Memory ReadParameter Min Max Unit Memory Write Parameter Min Max Unit Serial Ports Parameter Min Max Unit Idma Address Latch Parameter Min Max Unit Idma Write, Short Write Cycle 28.8 MHzParameter Min Max Idma Write, Short Write Cycle Parameter Min Max Unit Idma Write, Long Write Cycle 28.8 MHz Parameter Min Max Unit Idma Read, Long Read Cycle Parameter Min Max Unit Idma Read, Long Read Cycle28.8 MHz Parameter Min Max Unit Idma Read, Short Read Cycle Parameter Min Max Unit Idma Read, Short Read CycleLead Tqfp Package Pinout Number Name PinOutline Dimensions Millimeters Inches Symbol MIN TYP MAXLead Pqfp Package Pinout PF0 160 Ordering Guide Page Page C2144-16-6/96
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