ADSP-2181/ADSP-2183
Program memory can store both instructions and data, permit- ting the
In addition to the address and data bus for external memory connection, the
An interface to low cost
The byte memory and I/O memory space interface supports slow memories and I/O
The
The two serial ports provide a complete synchronous serial inter- face with optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of operation.
Each port can generate an internal programmable serial clock or accept an external serial clock.
The
A programmable interval timer generates periodic interrupts. A
Serial Ports
The
Here is a brief list of the capabilities of the
•SPORTs are bidirectional and have a separate, double- buffered transmit and receive section.
•SPORTs can use an external serial clock or generate their own serial clock internally.
•SPORTs have independent framing for the receive and trans- mit sections. Sections run in a frameless mode or with frame synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of two pulse widths and timings.
21xx CORE
ADSP-2181/ADSP-2183 INTEGRATION
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| POWER |
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| DOWN |
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| CONTROL |
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| LOGIC |
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| INSTRUCTION | PROGRAM | DATA |
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| REGISTER | SRAM | SRAM |
| PROGRAMMABLE | 8 | ||
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| 16k × 24 | 16k × 16 | BYTE |
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| DMA | I/O |
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DATA | DATA |
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| CONTROLLER |
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ADDRESS | ADDRESS | PROGRAM |
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| FLAGS |
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GENERATOR | GENERATOR |
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SEQUENCER |
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#1 | #2 |
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| PMA BUS | 14 |
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| PMA BUS |
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| DMA BUS | 14 |
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| DMA BUS | MUX |
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| EXTERNAL | |
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| ADDRESS | |
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| BUS |
| PMD BUS | 24 |
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| PMD BUS |
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| EXTERNAL | |
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| DATA | |
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| BUS |
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| EXCHANGE |
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| DMD |
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| DMD BUS |
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| BUS |
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INPUT REGS | INPUT REGS | INPUT REGS |
| COMPANDING |
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| INTERNAL | 16 | |
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| CIRCUITRY |
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| DMA |
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ALU | MAC | SHIFTER |
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| TIMER |
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| TRANSMIT REG |
| TRANSMIT REG |
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OUTPUT REGS | OUTPUT REGS | OUTPUT REGS | RECEIVE REG5 |
| RECEIVE REG |
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| SERIAL |
| SERIAL |
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| PORT 0 |
| PORT 0 | INTERRUPTS |
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| R BUS | 5 |
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Figure 1. ADSP-2181/ADSP-2183 Block Diagram
REV. 0 |