Analog Devices ADSP-2183, ADSP-2181 manual Pin, Number Name

Page 32

ADSP-2181/ADSP-2183

TQFP Pin Configurations

TQFP		Pin						TQFP		Pin										TQFP		Pin					TQFP		Pin
Number	Name							Number	Name											Number	Name						Number	Name

1		IAL						33		A12										65		ECLK					97		D19
2		PF3						34		A13										66		ELOUT					98	D20
3		PF2						35		IRQE										67		ELIN					99		D21
4		PF1						36		MMAP										68		EINT					100		D22
5		PF0						37		PWD										69		EBR					101		D23
6		WR						38		IRQ2										70		BR					102		GND
7		RD						39		BMODE										71		EBG					103		IWR
8		IOMS						40		PWDACK										72		BG					104		IRD
9		BMS						41		IACK										73		VDD					105		IAD15
10		DMS						42		BGH										74		D0					106		IAD14
11		CMS						43		VDD										75		D1					107		IAD13
12		GND						44		GND										76		D2					108		IAD12
13		VDD						45		IRQL0										77		D3					109		IAD11
14		PMS						46		IRQL1										78		D4					110		IAD10
15		A0						47		FL0										79		GND					111	IAD9
16		A1						48		FL1										80		D5					112	IAD8
17		A2						49		FL2										81		D6					113	IAD7
18		A3						50		DT0										82		D7					114	IAD6
19		A4						51		TFS0										83		D8					115	VDD
20		A5						52		RFS0										84	D9						116	GND
21		A6						53		DR0										85	D10						117	IAD5
22		A7						54		SCLK0										86		D11					118	IAD4
23		XTAL						55		DT1/F0										87		D12					119	IAD3
24		CLKIN						56		TFS1/					IRQ1					88		D13					120	IAD2
25		GND						57		RFS1/IRQ0										89		D14					121	IAD1
26		CLKOUT						58	GND											90		GND					122	IAD0
27		GND						59		DR1/FI										91	VDD						123	PF7
28		VDD						60		SCLK1										92		GND					124	PF6
29		A8						61		ERESET										93		D15					125	PF5
30		A9						62		RESET										94		D16					126	PF4
31		A10						63		EMS										95		D17					127	GND
32		A11						64		EE										96	D18						128		IS

–32–

REV. 0

Image 32

Contents Functional Block Diagram General DescriptionADSP-2181/ADSP-2183 Architecture OverviewADSP-2181/ADSP-2183 Integration Pin Input Names Pins Output Function PIN DescriptionsInterrupt Vector Source of Interrupt Address HexHighest Priority Lowest PrioritySystem Interface ADSP-2181 ADSP-2183Pmovlay Memory A13 A120Memory Space Word Size Alignment Address Range Wait State RegisterInternal Booting Method Idma Port BootingSyntax IOaddr = dreg dreg = IOaddr Biased RoundingInstruction SET Description Designing AN EZ-ICE-COMPATIBLE SystemReset GND PM, DM, BM, IOM, & CMGrade Parameter Min Max Unit Grades Parameter Test Conditions Min Max UnitMemory Timing Specifications Frequency Dependency for Timing SpecificationsAbsolute Maximum Ratings ESD Sensitivity41C/W 10C/W 31C/W Package50C/W 2C/W 48C/W Capacitive Loading Test ConditionsADSP-2183-SPECIFICATIONS ADSP-2183 Timing Parameters Tqfp Delay Valid Output 28.8 MHz Parameter Min Max Clock Signals and Reset Parameter Min Max Unit Clock Signals and ResetControl Signals FI, or PFx Setup before Clkout Low1, 2, 3 25tCK + IRQx Flag Output Delay from Clkout Low5 25tCK +Parameter Min Max Unit Interrupts and Flag Flag Output Hold after Clkout Low5 5tCKParameter Min Max Unit Bus Request/Grant Parameter Min Max Unit Memory Read 28.8 MHz Parameter Min Max Unit Memory ReadParameter Min Max Unit Memory Write Parameter Min Max Unit Serial Ports Parameter Min Max Unit Idma Address Latch Parameter Min Max Idma Write, Short Write Cycle Parameter Min Max Unit Idma Write, Short Write Cycle28.8 MHz Parameter Min Max Unit Idma Write, Long Write Cycle Parameter Min Max Unit Idma Read, Long Read Cycle 28.8 MHz Parameter Min Max Unit Idma Read, Long Read CycleParameter Min Max Unit Idma Read, Short Read Cycle 28.8 MHz Parameter Min Max Unit Idma Read, Short Read CycleLead Tqfp Package Pinout Pin Number NameMillimeters Inches Symbol MIN TYP MAX Outline DimensionsLead Pqfp Package Pinout PF0 160 Ordering Guide Page Page C2144-16-6/96