Analog Devices ADSP-2183, ADSP-2181 manual

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Contents Functional Block Diagram General DescriptionADSP-2181/ADSP-2183 Architecture OverviewADSP-2181/ADSP-2183 Integration Pin Input Names Pins Output Function PIN DescriptionsHighest Priority Interrupt VectorSource of Interrupt Address Hex Lowest PrioritySystem Interface ADSP-2181 ADSP-2183Pmovlay Memory A13 A120Memory Space Word Size Alignment Address Range Wait State RegisterInternal Booting Method Idma Port BootingInstruction SET Description Syntax IOaddr = dreg dreg = IOaddrBiased Rounding Designing AN EZ-ICE-COMPATIBLE SystemReset GND PM, DM, BM, IOM, & CMGrade Parameter Min Max Unit Grades Parameter Test Conditions Min Max UnitAbsolute Maximum Ratings Memory Timing SpecificationsFrequency Dependency for Timing Specifications ESD Sensitivity41C/W 10C/W 31C/W Package50C/W 2C/W 48C/W Capacitive Loading Test ConditionsADSP-2183-SPECIFICATIONS ADSP-2183 Timing Parameters Tqfp Delay Valid Output 28.8 MHz Parameter Min Max Clock Signals and Reset Parameter Min Max Unit Clock Signals and ResetControl Signals Parameter Min Max Unit Interrupts and Flag FI, or PFx Setup before Clkout Low1, 2, 3 25tCK + IRQxFlag Output Delay from Clkout Low5 25tCK + Flag Output Hold after Clkout Low5 5tCKParameter Min Max Unit Bus Request/Grant Parameter Min Max Unit Memory Read 28.8 MHz Parameter Min Max Unit Memory ReadParameter Min Max Unit Memory Write Parameter Min Max Unit Serial Ports Parameter Min Max Unit Idma Address Latch Parameter Min Max Idma Write, Short Write Cycle Parameter Min Max Unit Idma Write, Short Write Cycle28.8 MHz Parameter Min Max Unit Idma Write, Long Write Cycle Parameter Min Max Unit Idma Read, Long Read Cycle 28.8 MHz Parameter Min Max Unit Idma Read, Long Read CycleParameter Min Max Unit Idma Read, Short Read Cycle 28.8 MHz Parameter Min Max Unit Idma Read, Short Read CycleLead Tqfp Package Pinout Pin Number NameMillimeters Inches Symbol MIN TYP MAX Outline DimensionsLead Pqfp Package Pinout PF0 160 Ordering Guide Page Page C2144-16-6/96