Analog Devices ADSP-2183, ADSP-2181 manual Parameter Min Max Unit Bus Request/Grant

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ADSP-2181/ADSP-2183

ADSP-2181/ADSP-2183

Parameter

Min

Max

Unit

Bus Request/Grant

Timing Requirements:

tBH

Hold after CLKOUT High1

0.25tCK + 2

ns

BR

tBS

BR

Setup before CLKOUT Low1

0.25tCK + 17

ns

Switching Characteristics:

tSD

CLKOUT High to

xMS

,

0.25tCK + 10

ns

RD

,

WR

Disable

tSDB

xMS

,

RD

,

WR

Disable to BG Low

0

ns

tSE

BG

High to

xMS

,

RD

,

WR

Enable

0

ns

tSEC

xMS, RD, WR

tSDBH

Enable to CLKOUT High

0.25tCK – 7

ns

xMS

,

RD

,

WR

Low2

Disable to

BGH

0

ns

tSEH

BGH

High to

xMS

,

RD

,

WR

Enable2

0

ns

NOTES

xMS = PMS, DMS, CMS, IOMS, BMS

1BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.

2BGH is asserted when the bus is granted and the processor requires control of the bus to continue.

CLKOUT

BR

CLKOUT

PMS, DMS

BMS, RD WR

BG

BGH

tBH

tBS

tSD

tSDB

tSDBH

tSE

tSEC

tSEH

Figure 24. Bus Request–Bus Grant

–22–

REV. 0

Image 22

Contents Functional Block Diagram General DescriptionADSP-2181/ADSP-2183 Architecture OverviewADSP-2181/ADSP-2183 Integration Pin Input Names Pins Output Function PIN DescriptionsHighest Priority Interrupt VectorSource of Interrupt Address Hex Lowest PrioritySystem Interface ADSP-2181 ADSP-2183Pmovlay Memory A13 A120Internal Address Range Wait State RegisterMemory Space Word Size Alignment Booting Method Idma Port BootingInstruction SET Description Syntax IOaddr = dreg dreg = IOaddrBiased Rounding Designing AN EZ-ICE-COMPATIBLE SystemReset GND PM, DM, BM, IOM, & CMGrade Parameter Min Max Unit Grades Parameter Test Conditions Min Max UnitAbsolute Maximum Ratings Memory Timing SpecificationsFrequency Dependency for Timing Specifications ESD Sensitivity50C/W 2C/W 48C/W Package41C/W 10C/W 31C/W Capacitive Loading Test ConditionsADSP-2183-SPECIFICATIONS ADSP-2183 Timing Parameters Tqfp Delay Valid Output Control Signals Parameter Min Max Unit Clock Signals and Reset28.8 MHz Parameter Min Max Clock Signals and Reset Parameter Min Max Unit Interrupts and Flag FI, or PFx Setup before Clkout Low1, 2, 3 25tCK + IRQxFlag Output Delay from Clkout Low5 25tCK + Flag Output Hold after Clkout Low5 5tCKParameter Min Max Unit Bus Request/Grant Parameter Min Max Unit Memory Read 28.8 MHz Parameter Min Max Unit Memory ReadParameter Min Max Unit Memory Write Parameter Min Max Unit Serial Ports Parameter Min Max Unit Idma Address Latch 28.8 MHz Parameter Min Max Unit Idma Write, Short Write CycleParameter Min Max Idma Write, Short Write Cycle Parameter Min Max Unit Idma Write, Long Write Cycle Parameter Min Max Unit Idma Read, Long Read Cycle 28.8 MHz Parameter Min Max Unit Idma Read, Long Read CycleParameter Min Max Unit Idma Read, Short Read Cycle 28.8 MHz Parameter Min Max Unit Idma Read, Short Read CycleLead Tqfp Package Pinout Pin Number NameMillimeters Inches Symbol MIN TYP MAX Outline DimensionsLead Pqfp Package Pinout PF0 160 Ordering Guide Page Page C2144-16-6/96