Analog Devices ADSP-2181, ADSP-2183 manual Parameter Min Max Unit Interrupts and Flag

Page 21

ADSP-2181/ADSP-2183

ADSP-2181

Parameter

 

 

Min

Max

Unit

 

 

 

 

 

Interrupts and Flag

 

 

 

Timing Requirements:

 

 

 

tIFS

 

, FI, or PFx Setup before CLKOUT Low1, 2, 3, 4

0.25tCK + 15

 

ns

IRQx

 

tIFH

IRQx

, FI, or PFx Hold after CLKOUT High1, 2, 3, 4

0.25tCK

 

ns

Switching Characteristics:

 

 

 

tFOH

Flag Output Hold after CLKOUT Low5

0.5tCK – 7

 

ns

tFOD

Flag Output Delay from CLKOUT Low5

 

0.25tCK + 5

ns

ADSP-2183

 

 

 

28.8 MHz

 

 

Parameter

 

 

Min

Max

Unit

 

 

 

 

 

Interrupts and Flag

 

 

 

Timing Requirements:

 

 

 

tIFS

 

, FI, or PFx Setup before CLKOUT Low1, 2, 3, 4

0.25tCK + 15

 

ns

IRQx

 

tIFH

IRQx

, FI, or PFx Hold after CLKOUT High1, 2, 3, 4

0.25tCK

 

ns

Switching Characteristics:

 

 

 

tFOH

Flag Output Hold after CLKOUT Low5

0.5tCK – 7

 

ns

tFOD

Flag Output Delay from CLKOUT Low5

 

0.25tCK + 6

ns

NOTES

1If IRQx and FI inputs meet tIFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the User’s Manual for further information on interrupt servicing.)

2Edge-sensitive interrupts require pulse widths greater than 10 ns; level-sensitive interrupts must be held low until serviced.

3IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE. 4PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.

5Flag outputs = PFx, FL0, FL1, FL2, Flag_out4.

CLKOUT

FLAG

OUTPUTS

IRQx

FI

PFx

tFOD

tFOH

tIFH

tIFS

Figure 23. Interrupts and Flags

REV. 0

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Contents General Description Functional Block DiagramArchitecture Overview ADSP-2181/ADSP-2183ADSP-2181/ADSP-2183 Integration PIN Descriptions Pin Input Names Pins Output FunctionSource of Interrupt Address Hex Interrupt VectorHighest Priority Lowest PriorityADSP-2181 ADSP-2183 System InterfaceMemory A13 A120 PmovlayAddress Range Wait State Register InternalMemory Space Word Size Alignment Idma Port Booting Booting MethodBiased Rounding Syntax IOaddr = dreg dreg = IOaddrInstruction SET Description Designing AN EZ-ICE-COMPATIBLE SystemPM, DM, BM, IOM, & CM Reset GNDGrades Parameter Test Conditions Min Max Unit Grade Parameter Min Max UnitFrequency Dependency for Timing Specifications Memory Timing SpecificationsAbsolute Maximum Ratings ESD SensitivityPackage 50C/W 2C/W 48C/W41C/W 10C/W 31C/W Test Conditions Capacitive LoadingADSP-2183-SPECIFICATIONS ADSP-2183 Timing Parameters Tqfp Delay Valid Output Parameter Min Max Unit Clock Signals and Reset Control Signals28.8 MHz Parameter Min Max Clock Signals and Reset Flag Output Delay from Clkout Low5 25tCK + FI, or PFx Setup before Clkout Low1, 2, 3 25tCK + IRQxParameter Min Max Unit Interrupts and Flag Flag Output Hold after Clkout Low5 5tCKParameter Min Max Unit Bus Request/Grant 28.8 MHz Parameter Min Max Unit Memory Read Parameter Min Max Unit Memory ReadParameter Min Max Unit Memory Write Parameter Min Max Unit Serial Ports Parameter Min Max Unit Idma Address Latch Parameter Min Max Unit Idma Write, Short Write Cycle 28.8 MHzParameter Min Max Idma Write, Short Write Cycle Parameter Min Max Unit Idma Write, Long Write Cycle 28.8 MHz Parameter Min Max Unit Idma Read, Long Read Cycle Parameter Min Max Unit Idma Read, Long Read Cycle28.8 MHz Parameter Min Max Unit Idma Read, Short Read Cycle Parameter Min Max Unit Idma Read, Short Read CycleLead Tqfp Package Pinout Number Name PinOutline Dimensions Millimeters Inches Symbol MIN TYP MAXLead Pqfp Package Pinout PF0 160 Ordering Guide Page Page C2144-16-6/96
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