Analog Devices ADSP-2181, ADSP-2183 Millimeters Inches Symbol MIN TYP MAX, Outline Dimensions

Page 33

ADSP-2181/ADSP-2183

OUTLINE DIMENSIONS

128-Lead Metric Thin Plastic Quad Flatpack (TQFP)

A

L

SEATING

PLANE

 

D

 

D1

 

D3

128

103

1

102

TOP VIEW

 

 

E3 E1 E

 

 

 

 

(PINS DOWN)

D

A1 A2

38

39

65 64

Be

 

MILLIMETERS

 

INCHES

 

SYMBOL

MIN

TYP

MAX

MIN

TYP

MAX

 

 

 

 

 

 

 

A

 

 

1.60

 

0.063

 

 

 

 

 

 

 

 

A1

0.05

 

0.15

0.002

 

0.006

A2

1.30

1.40

1.50

0.051

0.055

0.059

 

 

 

 

 

 

 

D

15.75

16.00

16.25

0.620

0.630

0.640

 

 

 

 

 

 

 

D1

13.90

14.00

14.10

0.547

0.551

0.555

D3

 

12.50

12.58

 

0.492

0.495

E

21.75

22.00

22.25

0.856

0.866

0.876

 

 

 

 

 

 

 

E1

19.90

20.00

20.10

0.783

0.787

0.792

 

 

 

 

 

 

 

E3

 

18.50

18.58

 

0.728

0.731

L

0.45

0.60

0.75

0.018

0.024

0.030

 

 

 

 

 

 

 

e

0.42

0.50

0.58

0.017

0.019

0.023

 

 

 

 

 

 

 

B

0.17

0.22

0.27

0.007

0.009

0.011

 

 

 

 

 

 

 

D

 

 

0.10

 

 

0.004

 

 

 

 

 

REV. 0

–33–

Image 33
Contents General Description Functional Block DiagramArchitecture Overview ADSP-2181/ADSP-2183ADSP-2181/ADSP-2183 Integration PIN Descriptions Pin Input Names Pins Output FunctionSource of Interrupt Address Hex Interrupt VectorHighest Priority Lowest PriorityADSP-2181 ADSP-2183 System InterfaceMemory A13 A120 PmovlayAddress Range Wait State Register InternalMemory Space Word Size Alignment Idma Port Booting Booting MethodBiased Rounding Syntax IOaddr = dreg dreg = IOaddrInstruction SET Description Designing AN EZ-ICE-COMPATIBLE SystemPM, DM, BM, IOM, & CM Reset GNDGrades Parameter Test Conditions Min Max Unit Grade Parameter Min Max UnitFrequency Dependency for Timing Specifications Memory Timing SpecificationsAbsolute Maximum Ratings ESD SensitivityPackage 50C/W 2C/W 48C/W41C/W 10C/W 31C/W Test Conditions Capacitive LoadingADSP-2183-SPECIFICATIONS ADSP-2183 Timing Parameters Tqfp Delay Valid Output Parameter Min Max Unit Clock Signals and Reset Control Signals28.8 MHz Parameter Min Max Clock Signals and Reset Flag Output Delay from Clkout Low5 25tCK + FI, or PFx Setup before Clkout Low1, 2, 3 25tCK + IRQxParameter Min Max Unit Interrupts and Flag Flag Output Hold after Clkout Low5 5tCKParameter Min Max Unit Bus Request/Grant 28.8 MHz Parameter Min Max Unit Memory Read Parameter Min Max Unit Memory ReadParameter Min Max Unit Memory Write Parameter Min Max Unit Serial Ports Parameter Min Max Unit Idma Address Latch Parameter Min Max Unit Idma Write, Short Write Cycle 28.8 MHzParameter Min Max Idma Write, Short Write Cycle Parameter Min Max Unit Idma Write, Long Write Cycle 28.8 MHz Parameter Min Max Unit Idma Read, Long Read Cycle Parameter Min Max Unit Idma Read, Long Read Cycle28.8 MHz Parameter Min Max Unit Idma Read, Short Read Cycle Parameter Min Max Unit Idma Read, Short Read CycleLead Tqfp Package Pinout Number Name PinOutline Dimensions Millimeters Inches Symbol MIN TYP MAXLead Pqfp Package Pinout PF0 160 Ordering Guide Page Page C2144-16-6/96