Analog Devices ADSP-2183, ADSP-2181 manual Parameter Min Max Unit Idma Write, Long Write Cycle

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ADSP-2181/ADSP-2183

ADSP-2181

Parameter							Min	Max	Unit

IDMA Write, Long Write Cycle
Timing Requirements:
tIKW	IACK	Low before Start of Write1					0		ns
tIKSU	IAD15–0 Data Setup before				IACK	Low2, 3	0.5tCK + 10		ns
tIKH	IAD15–0 Data Hold after IACK Low2, 3						2		ns
Switching Characteristics:
tIKLW	Start of Write to		IACK	Low4			1.5tCK		ns
tIKHW	Start of Write to IACK High							15	ns

ADSP-2183

									28.8 MHz
Parameter									Min	Max	Unit

IDMA Write, Long Write Cycle
Timing Requirements:
tIKW	IACK	Low before Start of Write1							0		ns
tIKSU	IAD15–0 Data Setup before					IACK		Low2, 3	0.5tCK + 10		ns
tIKH	IAD15–0 Data Hold after				IACK		Low2, 3		2		ns
Switching Characteristics:
tIKLW	Start of Write to		IACK	Low4					1.5tCK		ns
tIKHW	Start of Write to		IACK	High						17	ns

NOTES

1Start of Write = IS Low and IWR Low.

2If Write Pulse ends before IACK Low, use specifications tIDSU, tIDH.

3If Write Pulse ends after IACK Low, use specifications tIKSU, tIKH.

4This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the User’s Manual.

	tIKW
IACK
	tIKHW
	tIKLW
IS
IWR
	tIKSU	tIKH
		tIKH
IAD 15–0		DATA

Figure 30. IDMA Write, Long Write Cycle

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Contents Functional Block Diagram General DescriptionADSP-2181/ADSP-2183 Architecture OverviewADSP-2181/ADSP-2183 Integration Pin Input Names Pins Output Function PIN DescriptionsInterrupt Vector Source of Interrupt Address HexHighest Priority Lowest PrioritySystem Interface ADSP-2181 ADSP-2183Pmovlay Memory A13 A120Internal Address Range Wait State RegisterMemory Space Word Size Alignment Booting Method Idma Port BootingSyntax IOaddr = dreg dreg = IOaddr Biased RoundingInstruction SET Description Designing AN EZ-ICE-COMPATIBLE SystemReset GND PM, DM, BM, IOM, & CMGrade Parameter Min Max Unit Grades Parameter Test Conditions Min Max UnitMemory Timing Specifications Frequency Dependency for Timing SpecificationsAbsolute Maximum Ratings ESD Sensitivity50C/W 2C/W 48C/W Package41C/W 10C/W 31C/W Capacitive Loading Test ConditionsADSP-2183-SPECIFICATIONS ADSP-2183 Timing Parameters Tqfp Delay Valid Output Control Signals Parameter Min Max Unit Clock Signals and Reset28.8 MHz Parameter Min Max Clock Signals and Reset FI, or PFx Setup before Clkout Low1, 2, 3 25tCK + IRQx Flag Output Delay from Clkout Low5 25tCK +Parameter Min Max Unit Interrupts and Flag Flag Output Hold after Clkout Low5 5tCKParameter Min Max Unit Bus Request/Grant Parameter Min Max Unit Memory Read 28.8 MHz Parameter Min Max Unit Memory ReadParameter Min Max Unit Memory Write Parameter Min Max Unit Serial Ports Parameter Min Max Unit Idma Address Latch 28.8 MHz Parameter Min Max Unit Idma Write, Short Write CycleParameter Min Max Idma Write, Short Write Cycle Parameter Min Max Unit Idma Write, Long Write Cycle Parameter Min Max Unit Idma Read, Long Read Cycle 28.8 MHz Parameter Min Max Unit Idma Read, Long Read CycleParameter Min Max Unit Idma Read, Short Read Cycle 28.8 MHz Parameter Min Max Unit Idma Read, Short Read CycleLead Tqfp Package Pinout Pin Number NameMillimeters Inches Symbol MIN TYP MAX Outline DimensionsLead Pqfp Package Pinout PF0 160 Ordering Guide Page Page C2144-16-6/96