Analog Devices ADSP-2181, ADSP-2183 manual Parameter Min Max Unit Idma Read, Long Read Cycle

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ADSP-2181/ADSP-2183

ADSP-2181

Parameter			Min	Max	Unit

IDMA Read, Long Read Cycle
Timing Requirements:
tIKR	IACK	Low before Start of Read1	0		ns
tIRP	Duration of Read		15		ns
Switching Characteristics:
tIKHR	IACK	High after Start of Read1		15	ns
tIKDS	IAD15–0 Data Setup before IACK Low		0.5tCK –10		ns
tIKDH	IAD15–0 Data Hold after End of Read2		0		ns
tIKDD	IAD15–0 Data Disabled after End of Read2			10	ns
tIRDE	IAD15–0 Previous Data Enabled after Start of Read		0		ns
tIRDV	IAD15–0 Previous Data Valid after Start of Read			15	ns
tIRDH1	IAD15–0 Previous Data Hold after Start of Read (DM/PM1)3		2tCK –5		ns
tIRDH2	IAD15–0 Previous Data Hold after Start of Read (PM2)4		tCK–5		ns

ADSP-2183

			28.8 MHz
Parameter			Min	Max	Unit

IDMA Read, Long Read Cycle
Timing Requirements:
tIKR	IACK	Low before Start of Read1	0		ns
tIRP	Duration of Read		15		ns
Switching Characteristics:
tIKHR	IACK High after Start of Read1			17	ns
tIKDS	IAD15–0 Data Setup before IACK Low		0.5tCK –10		ns
tIKDH	IAD15–0 Data Hold after End of Read2		0		ns
tIKDD	IAD15–0 Data Disabled after End of Read2			10	ns
tIRDE	IAD15–0 Previous Data Enabled after Start of Read		0		ns
tIRDV	IAD15–0 Previous Data Valid after Start of Read			15	ns
tIRDH1	IAD15–0 Previous Data Hold after Start of Read (DM/PM1)3		2tCK –5		ns
tIRDH2	IAD15–0 Previous Data Hold after Start of Read (PM2)4		tCK–5		ns

NOTES

1Start of Read = IS Low and IRD Low.

2End of Read = IS High or IRD High. 3DM read or first half of PM read.

4Second half of PM read.

IACK

tIKHR tIKR

IS

tIRP

IRD

tIRDE

PREVIOUS

IAD 15–0

DATA

tIRDV

tIRDH

tIKDS

READ

DATA

tIKDH

tIKDD

Figure 31. IDMA Read, Long Read Cycle

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Contents General Description Functional Block DiagramArchitecture Overview ADSP-2181/ADSP-2183ADSP-2181/ADSP-2183 Integration PIN Descriptions Pin Input Names Pins Output FunctionSource of Interrupt Address Hex Interrupt VectorHighest Priority Lowest PriorityADSP-2181 ADSP-2183 System InterfaceMemory A13 A120 PmovlayMemory Space Word Size Alignment Address Range Wait State RegisterInternal Idma Port Booting Booting MethodBiased Rounding Syntax IOaddr = dreg dreg = IOaddrInstruction SET Description Designing AN EZ-ICE-COMPATIBLE SystemPM, DM, BM, IOM, & CM Reset GNDGrades Parameter Test Conditions Min Max Unit Grade Parameter Min Max UnitFrequency Dependency for Timing Specifications Memory Timing SpecificationsAbsolute Maximum Ratings ESD Sensitivity41C/W 10C/W 31C/W Package50C/W 2C/W 48C/W Test Conditions Capacitive LoadingADSP-2183-SPECIFICATIONS ADSP-2183 Timing Parameters Tqfp Delay Valid Output 28.8 MHz Parameter Min Max Clock Signals and Reset Parameter Min Max Unit Clock Signals and ResetControl Signals Flag Output Delay from Clkout Low5 25tCK + FI, or PFx Setup before Clkout Low1, 2, 3 25tCK + IRQxParameter Min Max Unit Interrupts and Flag Flag Output Hold after Clkout Low5 5tCKParameter Min Max Unit Bus Request/Grant 28.8 MHz Parameter Min Max Unit Memory Read Parameter Min Max Unit Memory ReadParameter Min Max Unit Memory Write Parameter Min Max Unit Serial Ports Parameter Min Max Unit Idma Address Latch Parameter Min Max Idma Write, Short Write Cycle Parameter Min Max Unit Idma Write, Short Write Cycle28.8 MHz Parameter Min Max Unit Idma Write, Long Write Cycle 28.8 MHz Parameter Min Max Unit Idma Read, Long Read Cycle Parameter Min Max Unit Idma Read, Long Read Cycle28.8 MHz Parameter Min Max Unit Idma Read, Short Read Cycle Parameter Min Max Unit Idma Read, Short Read CycleLead Tqfp Package Pinout Number Name PinOutline Dimensions Millimeters Inches Symbol MIN TYP MAXLead Pqfp Package Pinout PF0 160 Ordering Guide Page Page C2144-16-6/96