Freescale Semiconductor MPC860T user manual Glueless System Design, SIU Interrupt ConÞguration

Page 15

Freescale Semiconductor, Inc.

in memory management of transmit and receive data frames. External memory (DRAM) is inexpensive, and because BD rings in external memory have no inherent size limitations, memory management easily can be optimized to system needs.

1.4.2 SIU Interrupt ConÞguration

As shown in Figure 1-2, the SIU receives interrupts from internal sources, such as the FEC and other modules and external pins, IRQ[0Ð7].

System Interface Unit

SWT

 

 

 

 

 

 

 

 

 

NMI

 

 

 

 

GEN

 

IRQ[0Ð7]

Edge

 

IRQ0

 

 

 

 

.

Detector

 

 

 

.

Selector

 

 

 

.

 

 

NMI

 

 

 

Inc

 

 

 

DEC

Level 7

 

DEC

 

 

Semiconductor,

 

ControllerInterrupt

 

TB

Level 6

 

 

 

 

 

 

 

 

 

 

 

 

PowerPC

 

PIT

Level 5

 

Core

 

 

 

 

RTC

Level 4

 

 

 

 

 

 

 

 

 

 

IREQ

 

 

Level 3

 

 

 

PCMCIA

 

 

 

 

 

Level 2

 

 

Freescale

CPM Interrupt

 

 

 

Controller

Level 1

 

 

 

 

 

 

FEC

Level 0

 

 

 

 

 

 

 

Debug

 

 

Debug

 

 

 

 

 

Figure 1-2. MPC860T Interrupt Structure

 

Note that MII_TXCLK is shared with IRQ7 and becomes active as soon as the ETHER_EN bit in the Ethernet control register (ECNTRL) is set. IRQ7 must be masked in the system interface unit (SIU).

1.5 Glueless System Design

A fundamental design goal of the MPC8xx family was ease of interface to other system components. Examples of system design are located in the MPC860T userÕs manual.

MOTOROLAChapter 1.Overview1-5

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Contents
Freescale Semiconductor, Inc MPC860T Rev. D Fast Ethernet ControllerMotorola Literature Distribution Centers Contents Parallel I/O Ports Contents Paragraph Title Number Title Number IllustrationsViii MPC860T Rev. D Fast Ethernet Controller Supplement Tables Number Document Revision History Document Revision History Overview Lists signiÞcant changes between revisions of this documentComparison with the MPC860 Features1 MPC860TBlock Diagram Embedded PowerPC Processor Core System Interface Unit SIUFast Ethernet Controller SIU Interrupt ConÞguration Glueless System DesignInc Signal Descriptions FEC Signal DescriptionsName Pin Description Miitxer L1RSYNCBMiimdc RXD3MIITXD1 REJECT3MIITXD2 REJECT4Freescale Semiconductor, Inc This chapter discusses the operation of the FEC MII SignalsSignal Description FEC Signal Name Transceiver ConnectionRXD0 Serial Mode Connections to the External TransceiverFEC Frame Transmission TXD0FEC Frame Reception FEC Command Set CAM InterfaceEthernet Address Recognition Rcntrlprom = Hash Table AlgorithmCollision Handling Inter-Packet Gap TimeInternal and External Loopback Ethernet Error-Handling ProcedureTransmission Errors Reception ErrorsReception Errors Port D Pin Functions Chapter Parallel I/O PortsShows the port D pin assignments Enabling MII ModeSignal Function Port D RegistersCLK Sdma RegistersBits Describes Sdcr ÞeldsSdcr Field Descriptions FRZ Faid RAIDAddress Name Description Section Parameter RAMBrießy describes each enter in the FEC parameter RAM FEC Parameter RAM Memory MapRAM Perfect Match Address Low Register Addrlow Describes the Addrhigh Þelds RAM Perfect Match Address High AddrhighRAM Hash Table High Hashtablehigh Describes the Addrlow ÞeldsHashhigh RAM Hash Table Low HashtablelowDescribes Hashtablehigh Þelds Hashtablehigh Field DescriptionsDescribes Rdesstart Þelds Beginning of RxBD Ring RdesstartBeginning of TxBD Ring Xdesstart Describes Hashtablelow ÞeldsReceive Buffer Size Register Rbuffsize Describes Xdesstart ÞeldsXdesstart Field Descriptions Rbuffsize Field Descriptions Spare Fecpin Etheren Reset MUXEthernet Control Register Ecntrl Describes Rbuffsize ÞeldsFecpinmux Interrupt Event IEVENT/Interrupt Mask Register ImaskDescribes Ecntrl Þelds Ecntrl Field DescriptionsHberr Ethernet Interrupt Vector Register IvecRfint to notify at the end of frame 10. IEVENT/IMASK Field DescriptionsIlevel RxBD Active Register Rdesactive11 describes Ivec Þelds 11. Ivec Field DescriptionsTxBD Active Register Xdesactive 12 describes Rdesactive Þelds12. Rdesactive Field Descriptions MII Management Frame Register Miidata 13 describes Xdesactive Þelds13. Xdesactive Field Descriptions 14. Miidata Field Descriptions 14 describes Miidata ÞeldsDispreamble Miispeed MII Speed Control Register Miispeed15 describes Miispeed Þelds 15. Miispeed Field Descriptions17. Rbound Field Descriptions Fifo Receive Bound Register Rbound17 describes Rbound Þelds 16. Programming Examples for Miispeed Register18. Rfstart Field Descriptions Fifo Receive Start Register RfstartTransmit Watermark Register Xwmrk 18 describes Rñfstart ÞeldsFifo Transmit Start Register Xfstart 19 bit Þeld descriptions for Xwmrk19. Xwmrk Field Descriptions DATABO0 DATABO1 DESCBO0 DESCBO1 FC1 FC2 FC3 DMA Function Code Register Funcode20 describes Xfstart Þelds 20. Xfstart Field DescriptionsDescbo Receive Control Register Rcntrl21 describes Funcode Þelds 21. Funcode Field DescriptionsBcrej Receive Hash Register Rhash22 describes Rcntrl Þelds 22. Rcntrl Field Descriptions23. Rhash Field Descriptions Transmit Control Register Xcntrl22 describes Rhash Þelds 24 describes Xcntrl Þelds25. Hardware Initialization User Initialization before Setting EcntrletherenInitialization Sequence Hardware InitializationStep Description 27. User Initialization before Setting EcntrletherenDescriptor Controller Initialization User Initialization after Asserting EcntrletherenStep 27. User Initialization after Setting EcntrletherenBuffer Descriptors BDs Ethernet Receive Buffer Descriptor RxBDRO1 RxBD format is shown in Table27. Receive Buffer Descriptor RxBD Field Description RO1 RO2 Data LengthTO1 TO2 DEF CSL Ethernet Transmit Buffer Descriptor TxBD29 describes TxBD Þelds 29. Transmit Buffer Descriptor TxBD Field DescriptionsData Xcntrlhbc =Freescale Semiconductor, Inc Electrical SpeciÞcations DC Electrical CharacteristicsAC Electrical Characteristics MII Receive Signal Timing RXD30, RXDV, RXER, RxclkNum Characteristic Min Max Unit MII Transmit Signal Timing TXD30, TXEN, TXER, TxclkMII Receive Signal Timing MII Transmit Signal TimingCRS, COL MII Async Inputs Signal Timing CRS, COLMII Async Inputs Signal Timing Txen TxerMII Serial Management Channel Timing Shows the MII serial management channel timing diagramMPC860T Pin Assignments Following pins are marked as spare onFreescale Semiconductor, Inc Freescale Semiconductor, Inc For More Information On This Product
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