Freescale Semiconductor MPC860T user manual FEC Frame Reception

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Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

(I_EVENT[BABT] = 1); however, the entire frame is sent (no truncation). Whether buffer or frame interrupts can be generated is determined by I_MASK settings.

To pause transmission, set the graceful transmit stop bit, X_CNTRL[GTS]. When GTS is set, the FEC transmitter stops immediately if no transmission is in progress or continues transmission until the current frame either Þnishes or terminates with a collision. The GRA interrupt occurs when the graceful transmit stop operation completes. When GTS is cleared, the FEC resumes transmission with the next frame.

The FEC transmits bytes lsb Þrst.

3.3 FEC Frame Reception

FEC reception requires almost no host intervention. The FEC can perform address recognition, CRC checking, short-frame checking, and maximum frame-length checking.

When the software driver sets ECNTRL[ETHER_EN] and R_DES_ACTIVE in the CSR RxBD active register (R_DES_ACTIVE), the FEC receiver is enabled and immediately starts processing receive frames. When RX_DV is asserted, the receiver Þrst checks for a valid preamble/SFD (start frame delimiter) header, which is stripped and the frame is processed by the receiver. If a valid header is not found, the frame is ignored.

In serial mode, the Þrst 16 bit times of RX_D0 after RX_DV (RENA) is asserted are ignored. Following the Þrst 16 bit times the data sequence is checked for alternating ones and zeros.

¥If a 11 or 00 sequence is detected during bit times 17 to 21, the rest of the frame is ignored.

¥After bit time 21, the data sequence is monitored for a valid SFD (11). If a 00 is detected, the frame is rejected. If a 11 is detected, the preamble/SFD sequence is complete.

In MII mode, the receiver checks for at least one byte matching the SFD. Zero or more preamble bytes may occur, but if a 00 sequence is detected before the SFD byte, the frame is ignored.

After the Þrst eight bytes of the frame are passed to the receive FIFO, the FEC performs address recognition on the frame.

As soon as a collision window (64 bytes) of data is received and if address recognition has not rejected the frame, the FEC starts transferring the incoming frame to the RxBDÕs associated buffer. If the frame is a too short (due to collision) or is rejected by address recognition, no receive buffers are Þlled. Thus, no collision frames are presented to the user, except for any late collisions, which indicate serious LAN problems. When the data buffer has been Þlled, the FEC clears RxBD[E] and generates an RXB interrupt (if I_MASK[RBIEN] is set). If the incoming frame exceeds the length of the data buffer, the FEC fetches the next RxBD in the table and, if it is empty, continues transferring the rest

MOTOROLAChapter 3. Fast Ethernet Controller Operation3-3

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Freescale Semiconductor, Inc MPC860T Rev. D Fast Ethernet ControllerMotorola Literature Distribution Centers Contents Parallel I/O Ports Contents Paragraph Title Number Title Number IllustrationsViii MPC860T Rev. D Fast Ethernet Controller Supplement Tables Number Document Revision History Document Revision HistoryOverview Lists signiÞcant changes between revisions of this documentComparison with the MPC860 Features1 MPC860TBlock Diagram Fast Ethernet Controller Embedded PowerPC Processor CoreSystem Interface Unit SIU SIU Interrupt ConÞguration Glueless System DesignInc Name Pin Description Signal DescriptionsFEC Signal Descriptions Miitxer L1RSYNCBMiimdc RXD3 MIITXD1 REJECT3 MIITXD2 REJECT4Freescale Semiconductor, Inc This chapter discusses the operation of the FEC MII SignalsSignal Description FEC Signal Name Transceiver ConnectionRXD0 Serial Mode Connections to the External TransceiverFEC Frame Transmission TXD0FEC Frame Reception Ethernet Address Recognition FEC Command SetCAM Interface Rcntrlprom = Hash Table AlgorithmCollision Handling Inter-Packet Gap TimeInternal and External Loopback Ethernet Error-Handling ProcedureTransmission Errors Reception ErrorsReception Errors Port D Pin Functions Chapter Parallel I/O PortsShows the port D pin assignments Enabling MII ModeSignal Function Port D RegistersCLK Sdma RegistersBits Describes Sdcr ÞeldsSdcr Field Descriptions FRZ Faid RAIDAddress Name Description Section Parameter RAMBrießy describes each enter in the FEC parameter RAM FEC Parameter RAM Memory MapRAM Perfect Match Address Low Register Addrlow Describes the Addrhigh Þelds RAM Perfect Match Address High AddrhighRAM Hash Table High Hashtablehigh Describes the Addrlow ÞeldsHashhigh RAM Hash Table Low HashtablelowDescribes Hashtablehigh Þelds Hashtablehigh Field DescriptionsDescribes Rdesstart Þelds Beginning of RxBD Ring RdesstartBeginning of TxBD Ring Xdesstart Describes Hashtablelow ÞeldsXdesstart Field Descriptions Receive Buffer Size Register RbuffsizeDescribes Xdesstart Þelds Rbuffsize Field Descriptions Spare Fecpin Etheren Reset MUXEthernet Control Register Ecntrl Describes Rbuffsize ÞeldsFecpinmux Interrupt Event IEVENT/Interrupt Mask Register ImaskDescribes Ecntrl Þelds Ecntrl Field DescriptionsHberr Ethernet Interrupt Vector Register IvecRfint to notify at the end of frame 10. IEVENT/IMASK Field DescriptionsIlevel RxBD Active Register Rdesactive11 describes Ivec Þelds 11. Ivec Field Descriptions12. Rdesactive Field Descriptions TxBD Active Register Xdesactive12 describes Rdesactive Þelds 13. Xdesactive Field Descriptions MII Management Frame Register Miidata13 describes Xdesactive Þelds 14. Miidata Field Descriptions 14 describes Miidata ÞeldsDispreamble Miispeed MII Speed Control Register Miispeed15 describes Miispeed Þelds 15. Miispeed Field Descriptions17. Rbound Field Descriptions Fifo Receive Bound Register Rbound17 describes Rbound Þelds 16. Programming Examples for Miispeed Register18. Rfstart Field Descriptions Fifo Receive Start Register RfstartTransmit Watermark Register Xwmrk 18 describes Rñfstart Þelds19. Xwmrk Field Descriptions Fifo Transmit Start Register Xfstart19 bit Þeld descriptions for Xwmrk DATABO0 DATABO1 DESCBO0 DESCBO1 FC1 FC2 FC3 DMA Function Code Register Funcode20 describes Xfstart Þelds 20. Xfstart Field DescriptionsDescbo Receive Control Register Rcntrl21 describes Funcode Þelds 21. Funcode Field DescriptionsBcrej Receive Hash Register Rhash22 describes Rcntrl Þelds 22. Rcntrl Field Descriptions23. Rhash Field Descriptions Transmit Control Register Xcntrl22 describes Rhash Þelds 24 describes Xcntrl Þelds25. Hardware Initialization User Initialization before Setting EcntrletherenInitialization Sequence Hardware InitializationStep Description 27. User Initialization before Setting EcntrletherenDescriptor Controller Initialization User Initialization after Asserting EcntrletherenStep 27. User Initialization after Setting EcntrletherenBuffer Descriptors BDs Ethernet Receive Buffer Descriptor RxBDRO1 RxBD format is shown in Table27. Receive Buffer Descriptor RxBD Field Description RO1 RO2 Data LengthTO1 TO2 DEF CSL Ethernet Transmit Buffer Descriptor TxBD29 describes TxBD Þelds 29. Transmit Buffer Descriptor TxBD Field DescriptionsData Xcntrlhbc =Freescale Semiconductor, Inc Electrical SpeciÞcations DC Electrical CharacteristicsAC Electrical Characteristics MII Receive Signal Timing RXD30, RXDV, RXER, RxclkNum Characteristic Min Max Unit MII Transmit Signal Timing TXD30, TXEN, TXER, TxclkMII Receive Signal Timing MII Transmit Signal TimingCRS, COL MII Async Inputs Signal Timing CRS, COLMII Async Inputs Signal Timing Txen TxerMII Serial Management Channel Timing Shows the MII serial management channel timing diagramMPC860T Pin Assignments Following pins are marked as spare onFreescale Semiconductor, Inc Freescale Semiconductor, Inc For More Information On This Product
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