Freescale Semiconductor MPC860T user manual RxBD format is shown in Table, RO1 RO2 Data Length

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	0	1	2	3	4	5	6		7		8		9	10	11	12	13	14	15
+0	E	RO1	W	RO2	L	0		0		M	BC		MC	LG	NO	SH	CR	OV	TR

+2									DATA LENGTH

+4							RX BUFFER POINTER A[0Ð15]

+6						RX BUFFER POINTER A[16Ð31]

Figure 6-23. Receive Buffer Descriptor (RxBD)

The RxBD format is shown in Table 6-27.

Table 6-27. Receive Buffer Descriptor (RxBD) Field Description

	Bits	Name		Description

	0	E	Empty. Written by the FEC and user. Note that if the software driver sets RxBD[E], it should
			then write to R_DES_ACTIVE.
			0	The buffer associated with this BD is Þlled with received data, or reception was aborted due
				to an error. The status and length Þelds have been updated as required.
			1	The buffer associated with this BD is empty, or reception is in progress.

	1	RO1	Receive software ownership bit. Software use. This read/write bit is modiÞed by hardware and
			does not affect hardware.

	2	W	Wrap, written by user.
			0	The next BD is found in the consecutive location
			1	The next BD is found at the location deÞned in RAM.R_DES_START.

	3	RO2	Receive software ownership bit. Software use. This read/write bit is not modiÞed by hardware
			and does not affect hardware.

	4	L	Last in frame, written by FEC.
			0	The buffer is not the last in a frame.
			1	The buffer is the last in a frame.

	5Ð6	Ñ	Reserved.

	7	M	Miss, written by FEC.Set by the FEC for frames that were accepted in promiscuous mode but
			were ßagged as a miss by the internal address recognition. Thus, while promiscuous mode is
			being used, the user can use the M bit to quickly determine whether the frame was destined to
			this station. This bit is valid only if both the L bit and PROM bit are set.
			0	The frame was received because of an address recognition hit.
			1	The frame was received because of promiscuous mode.

	8	BC	Set if the DA is broadcast.

	9	MC	Set if the DA is multicast and not broadcast.

	10	LG	Rx frame length violation, written by FEC. The frame length exceeds the value of
			MAX_FRAME_LENGTH in the bytes. The hardware truncates frames exceeding 2047 bytes so
			as not to overßow receive buffers This bit is valid only if the L bit is set. (Note that the Þrst
			revision of the MPC860T (mask #H56S) must not be given frames in excess of 2047 as it will
			not truncate frames.)

	11	NO	Rx nonoctet-aligned frame, written by FEC. A frame that contained a number of bits not
			divisible by 8 was received and the CRC check that occurred at the preceding byte boundary
			generated an error. NO is valid only if the L bit is set. If this bit is set the CR bit is not set.

	12	SH	Short frame, written by FEC. A frame length that was less than the minimum deÞned for this
			channel was recognized.Note that the MPC860T does not support SH, which is always zero.

	13	CR	Rx CRC error, written by FEC. This frame contains a CRC error and is an integral number of
			octets in length. This bit is valid only if the L bit is set.

MOTOROLAChapter 6.Programming Model6-25

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Contents Freescale Semiconductor, Inc MPC860T Rev. D Fast Ethernet ControllerMotorola Literature Distribution Centers Contents Parallel I/O Ports Contents Paragraph Title Number Title Number IllustrationsViii MPC860T Rev. D Fast Ethernet Controller Supplement Tables Number Overview Document Revision HistoryLists signiÞcant changes between revisions of this document Document Revision HistoryComparison with the MPC860 Features1 MPC860TBlock Diagram Embedded PowerPC Processor Core System Interface Unit SIUFast Ethernet Controller SIU Interrupt ConÞguration Glueless System DesignInc Signal Descriptions FEC Signal DescriptionsName Pin Description Miimdc L1RSYNCBRXD3 MiitxerMIITXD2 REJECT3REJECT4 MIITXD1Freescale Semiconductor, Inc Signal Description FEC Signal Name MII SignalsTransceiver Connection This chapter discusses the operation of the FECFEC Frame Transmission Serial Mode Connections to the External TransceiverTXD0 RXD0FEC Frame Reception FEC Command Set CAM InterfaceEthernet Address Recognition Rcntrlprom = Hash Table AlgorithmCollision Handling Inter-Packet Gap TimeTransmission Errors Ethernet Error-Handling ProcedureReception Errors Internal and External LoopbackReception Errors Port D Pin Functions Chapter Parallel I/O PortsSignal Function Enabling MII ModePort D Registers Shows the port D pin assignmentsCLK Sdma RegistersSdcr Field Descriptions Describes Sdcr ÞeldsFRZ Faid RAID BitsBrießy describes each enter in the FEC parameter RAM Parameter RAMFEC Parameter RAM Memory Map Address Name Description SectionRAM Perfect Match Address Low Register Addrlow RAM Hash Table High Hashtablehigh RAM Perfect Match Address High AddrhighDescribes the Addrlow Þelds Describes the Addrhigh ÞeldsDescribes Hashtablehigh Þelds RAM Hash Table Low HashtablelowHashtablehigh Field Descriptions HashhighBeginning of TxBD Ring Xdesstart Beginning of RxBD Ring RdesstartDescribes Hashtablelow Þelds Describes Rdesstart ÞeldsReceive Buffer Size Register Rbuffsize Describes Xdesstart ÞeldsXdesstart Field Descriptions Ethernet Control Register Ecntrl Spare Fecpin Etheren Reset MUXDescribes Rbuffsize Þelds Rbuffsize Field DescriptionsDescribes Ecntrl Þelds Interrupt Event IEVENT/Interrupt Mask Register ImaskEcntrl Field Descriptions FecpinmuxRfint to notify at the end of frame Ethernet Interrupt Vector Register Ivec10. IEVENT/IMASK Field Descriptions Hberr11 describes Ivec Þelds RxBD Active Register Rdesactive11. Ivec Field Descriptions IlevelTxBD Active Register Xdesactive 12 describes Rdesactive Þelds12. Rdesactive Field Descriptions MII Management Frame Register Miidata 13 describes Xdesactive Þelds13. Xdesactive Field Descriptions 14. Miidata Field Descriptions 14 describes Miidata Þelds15 describes Miispeed Þelds MII Speed Control Register Miispeed15. Miispeed Field Descriptions Dispreamble Miispeed17 describes Rbound Þelds Fifo Receive Bound Register Rbound16. Programming Examples for Miispeed Register 17. Rbound Field DescriptionsTransmit Watermark Register Xwmrk Fifo Receive Start Register Rfstart18 describes Rñfstart Þelds 18. Rfstart Field DescriptionsFifo Transmit Start Register Xfstart 19 bit Þeld descriptions for Xwmrk19. Xwmrk Field Descriptions 20 describes Xfstart Þelds DMA Function Code Register Funcode20. Xfstart Field Descriptions DATABO0 DATABO1 DESCBO0 DESCBO1 FC1 FC2 FC321 describes Funcode Þelds Receive Control Register Rcntrl21. Funcode Field Descriptions Descbo22 describes Rcntrl Þelds Receive Hash Register Rhash22. Rcntrl Field Descriptions Bcrej22 describes Rhash Þelds Transmit Control Register Xcntrl24 describes Xcntrl Þelds 23. Rhash Field DescriptionsInitialization Sequence User Initialization before Setting EcntrletherenHardware Initialization 25. Hardware InitializationDescriptor Controller Initialization 27. User Initialization before Setting EcntrletherenUser Initialization after Asserting Ecntrletheren Step DescriptionBuffer Descriptors BDs 27. User Initialization after Setting EcntrletherenEthernet Receive Buffer Descriptor RxBD Step27. Receive Buffer Descriptor RxBD Field Description RxBD format is shown in TableRO1 RO2 Data Length RO129 describes TxBD Þelds Ethernet Transmit Buffer Descriptor TxBD29. Transmit Buffer Descriptor TxBD Field Descriptions TO1 TO2 DEF CSLData Xcntrlhbc =Freescale Semiconductor, Inc AC Electrical Characteristics DC Electrical CharacteristicsMII Receive Signal Timing RXD30, RXDV, RXER, Rxclk Electrical SpeciÞcationsMII Receive Signal Timing MII Transmit Signal Timing TXD30, TXEN, TXER, TxclkMII Transmit Signal Timing Num Characteristic Min Max UnitMII Async Inputs Signal Timing MII Async Inputs Signal Timing CRS, COLTxen Txer CRS, COLMII Serial Management Channel Timing Shows the MII serial management channel timing diagramMPC860T Pin Assignments Following pins are marked as spare onFreescale Semiconductor, Inc Freescale Semiconductor, Inc For More Information On This Product