Signal Descriptions | Freescale Semiconductor MPC860T specification

Freescale Semiconductor MPC860T user manual FEC Signal Descriptions, Name Pin Description

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Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc...

Chapter 2 FEC External Signals

This chapter contains brief descriptions of the MPC860T FEC input and output signals in their functional groups.

2.1 Signal Descriptions

The MPC860T system bus signals consist of all the lines that interface with the external bus. Many of these lines perform different functions, depending on how the user assigns them. The input and output signals, shown in Table 2-1, are identiÞed by their abbreviated names.

		Table 2-1. FEC Signal Descriptions

Name	Pin			Description
Name	Number			Description
	Number

	W15	Interrupt request 7ÑThis input is one of the eight external lines that can request (by means
IRQ7	W15
MII_TX_CLK		of the internal Interrupt Controller) a service routine from the core. See description of
		MII_TXCLK for information about masking			IRQ7.

		MII transmit clockÑInput clock that provides the timing reference for TX_EN, TXD, and
		TX_ER. Note that MII_TXCLK becomes active as soon as the ETHER_EN bit in the Ethernet
		control register (ECNTRL) is set.		must be masked in the system interface unit (SIU).
		control register (ECNTRL) is set.	IRQ7	must be masked in the system interface unit (SIU).

PD[15]	U17	General-purpose I/O port D bit 15ÑThis is bit 15 of the general-purpose I/O port D.
L1TSYNCA
L1TSYNCA		Transmit data sync signal for TDM channel A
MII_RXD[3]		Transmit data sync signal for TDM channel A
MII_RXD[3]

		MII receive data 3ÑInput signal RXD[3] represents bit 3 of the nibble of data to be
		transferred from the PHY to the MAC when RX_DV is asserted.

PD[14]	V19	General-purpose I/O port D bit 14ÑThis is bit 14 of the general-purpose I/O port D.
L1RSYNCA
L1RSYNCA		Input receive data sync signal to the TDM channel A
MII_RXD[2]		Input receive data sync signal to the TDM channel A
MII_RXD[2]

		MII receive data 2ÑInput signal RXD[2] represents bit 2 of the nibble of data to be
		transferred from the PHY to the MAC when RX_DV is asserted.

PD[13]	V18	General-purpose I/O port D bit 13ÑThis is bit 13 of the general-purpose I/O port D.
L1TSYNCB
L1TSYNCB		Transmit data sync signal for TDM channel B
MII_RXD[1]		Transmit data sync signal for TDM channel B
MII_RXD[1]

		MII receive data 1ÑInput signal RXD[1] represents bit 1 of the nibble of data to be
		transferred from the PHY to the MAC when RX_DV is asserted.

MOTOROLAChapter 2. FEC External Signals2-1

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Contents

Freescale Semiconductor, Inc MPC860T Rev. D Fast Ethernet ControllerMotorola Literature Distribution Centers Contents Parallel I/O Ports Contents Paragraph Title Number Title Number IllustrationsViii MPC860T Rev. D Fast Ethernet Controller Supplement Tables Number Overview Document Revision HistoryLists signiÞcant changes between revisions of this document Document Revision HistoryComparison with the MPC860 Features 1 MPC860TBlock Diagram Fast Ethernet Controller Embedded PowerPC Processor CoreSystem Interface Unit SIU SIU Interrupt ConÞguration Glueless System DesignInc Name Pin Description Signal DescriptionsFEC Signal Descriptions Miimdc L1RSYNCBRXD3 MiitxerMIITXD2 REJECT3REJECT4 MIITXD1Freescale Semiconductor, Inc Signal Description FEC Signal Name MII SignalsTransceiver Connection This chapter discusses the operation of the FECFEC Frame Transmission Serial Mode Connections to the External TransceiverTXD0 RXD0FEC Frame Reception Ethernet Address Recognition FEC Command SetCAM Interface Rcntrlprom = Hash Table AlgorithmCollision Handling Inter-Packet Gap TimeTransmission Errors Ethernet Error-Handling ProcedureReception Errors Internal and External LoopbackReception Errors Port D Pin Functions Chapter Parallel I/O PortsSignal Function Enabling MII ModePort D Registers Shows the port D pin assignmentsCLK Sdma RegistersSdcr Field Descriptions Describes Sdcr ÞeldsFRZ Faid RAID BitsBrießy describes each enter in the FEC parameter RAM Parameter RAMFEC Parameter RAM Memory Map Address Name Description SectionRAM Perfect Match Address Low Register Addrlow RAM Hash Table High Hashtablehigh RAM Perfect Match Address High AddrhighDescribes the Addrlow Þelds Describes the Addrhigh ÞeldsDescribes Hashtablehigh Þelds RAM Hash Table Low HashtablelowHashtablehigh Field Descriptions HashhighBeginning of TxBD Ring Xdesstart Beginning of RxBD Ring RdesstartDescribes Hashtablelow Þelds Describes Rdesstart ÞeldsXdesstart Field Descriptions Receive Buffer Size Register RbuffsizeDescribes Xdesstart Þelds Ethernet Control Register Ecntrl Spare Fecpin Etheren Reset MUXDescribes Rbuffsize Þelds Rbuffsize Field DescriptionsDescribes Ecntrl Þelds Interrupt Event IEVENT/Interrupt Mask Register ImaskEcntrl Field Descriptions FecpinmuxRfint to notify at the end of frame Ethernet Interrupt Vector Register Ivec10. IEVENT/IMASK Field Descriptions Hberr11 describes Ivec Þelds RxBD Active Register Rdesactive11. Ivec Field Descriptions Ilevel12. Rdesactive Field Descriptions TxBD Active Register Xdesactive12 describes Rdesactive Þelds 13. Xdesactive Field Descriptions MII Management Frame Register Miidata13 describes Xdesactive Þelds 14. Miidata Field Descriptions 14 describes Miidata Þelds15 describes Miispeed Þelds MII Speed Control Register Miispeed15. Miispeed Field Descriptions Dispreamble Miispeed17 describes Rbound Þelds Fifo Receive Bound Register Rbound16. Programming Examples for Miispeed Register 17. Rbound Field DescriptionsTransmit Watermark Register Xwmrk Fifo Receive Start Register Rfstart18 describes Rñfstart Þelds 18. Rfstart Field Descriptions19. Xwmrk Field Descriptions Fifo Transmit Start Register Xfstart19 bit Þeld descriptions for Xwmrk 20 describes Xfstart Þelds DMA Function Code Register Funcode20. Xfstart Field Descriptions DATABO0 DATABO1 DESCBO0 DESCBO1 FC1 FC2 FC321 describes Funcode Þelds Receive Control Register Rcntrl21. Funcode Field Descriptions Descbo22 describes Rcntrl Þelds Receive Hash Register Rhash22. Rcntrl Field Descriptions Bcrej22 describes Rhash Þelds Transmit Control Register Xcntrl24 describes Xcntrl Þelds 23. Rhash Field DescriptionsInitialization Sequence User Initialization before Setting EcntrletherenHardware Initialization 25. Hardware InitializationDescriptor Controller Initialization 27. User Initialization before Setting EcntrletherenUser Initialization after Asserting Ecntrletheren Step DescriptionBuffer Descriptors BDs 27. User Initialization after Setting EcntrletherenEthernet Receive Buffer Descriptor RxBD Step27. Receive Buffer Descriptor RxBD Field Description RxBD format is shown in TableRO1 RO2 Data Length RO129 describes TxBD Þelds Ethernet Transmit Buffer Descriptor TxBD29. Transmit Buffer Descriptor TxBD Field Descriptions TO1 TO2 DEF CSLData Xcntrlhbc =Freescale Semiconductor, Inc AC Electrical Characteristics DC Electrical CharacteristicsMII Receive Signal Timing RXD30, RXDV, RXER, Rxclk Electrical SpeciÞcationsMII Receive Signal Timing MII Transmit Signal Timing TXD30, TXEN, TXER, TxclkMII Transmit Signal Timing Num Characteristic Min Max UnitMII Async Inputs Signal Timing MII Async Inputs Signal Timing CRS, COLTxen Txer CRS, COLMII Serial Management Channel Timing Shows the MII serial management channel timing diagramMPC860T Pin Assignments Following pins are marked as spare onFreescale Semiconductor, Inc Freescale Semiconductor, Inc For More Information On This Product

Freescale Semiconductor MPC860T user manual FEC Signal Descriptions, Name Pin Description

Freescale Semiconductor, Inc.

Chapter 2

FEC External Signals

2.1 Signal Descriptions

Table 2-1. FEC Signal Descriptions

Name

Pin

Description

MII_TX_CLK

MII_RXD[3]

MII_RXD[2]

MII_RXD[1]