Freescale Semiconductor MPC860T user manual describes Miidata Þelds, Miidata Field Descriptions

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Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

Bits	0		1	2		3	4	5	6	7	8	9	10	11	12	13	14		15

Field		ST			OP				PA					RA				TA

Reset										UndeÞned

R/W										Read/write

Addr										0xE80

Bits	16		17	18		19	20	21	22	23	24	25	26	27	28	29	30		31

Field										DATA

Reset										UndeÞned

R/W										Read/write

Addr										0xE82

Figure 6-13. MII_DATA Register

Table 6-14 describes MII_DATA Þelds.

		Table 6-14. MII_DATA Field Descriptions

Bits	Name	Description

0Ð1	ST	Start of frame delimiter. Must be programmed to 01 for a valid MII management frame.

2Ð3	OP	Operation code. Must be 10 (read) or 01(write) to generate a valid MII management frame.

4Ð8	PA	PHY address. SpeciÞes one of up to 32 attached PHY devices.

9Ð13	RA	Register address. SpeciÞes one of up to 32 registers within the speciÞed PHY device.

14Ð15	TA	Turnaround. Must be programmed to 10 to generate a valid MII management frame.

16Ð31	DATA	Management frame data. Field for data to be written to or read from PHY register.

To read or write on the MII management interface, MII_DATA is written by the user. To generate a valid read or write management frame, ST must be 01, OP must be 01 (management register write frame) or 10 (management register read frame), and TA must be 10.

To generate an 802.3-compliant MII management interface write frame (write to a PHY register) the user must write {01 01 PHYAD REGAD 10 DATA} to MII_DATA. Writing this pattern causes the control logic to shift data out of MII_DATA following a preamble generated by the control state machine. When the write management frame operation completes, the MII_DATAIO_COMPL interrupt is generated. At this time the contents of MII_DATA match the original value written.

To generate an MII management interface read frame (read a PHY register), the user must write {01 10 PHYAD REGAD 10 XXXX} to MII_DATA, (the content of the DATA Þeld is a donÕt care). Writing this pattern causes the control logic to shift data out of MII_DATA following a preamble generated by the control state machine. During this time, the contents of MII_DATA are serially shifted and are unpredictable if read by the user. An MII_DATAIO_COMPL interrupt is generated when the read management frame operation

MOTOROLAChapter 6.Programming Model6-13

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Contents Freescale Semiconductor, Inc MPC860T Rev. D Fast Ethernet ControllerMotorola Literature Distribution Centers Contents Parallel I/O Ports Contents Paragraph Title Number Title Number IllustrationsViii MPC860T Rev. D Fast Ethernet Controller Supplement Tables Number Overview Document Revision HistoryLists signiÞcant changes between revisions of this document Document Revision HistoryComparison with the MPC860 Features1 MPC860TBlock Diagram Embedded PowerPC Processor Core System Interface Unit SIUFast Ethernet Controller SIU Interrupt ConÞguration Glueless System DesignInc Signal Descriptions FEC Signal DescriptionsName Pin Description Miimdc L1RSYNCBRXD3 MiitxerMIITXD2 REJECT3REJECT4 MIITXD1Freescale Semiconductor, Inc Signal Description FEC Signal Name MII SignalsTransceiver Connection This chapter discusses the operation of the FECFEC Frame Transmission Serial Mode Connections to the External TransceiverTXD0 RXD0FEC Frame Reception FEC Command Set CAM InterfaceEthernet Address Recognition Rcntrlprom = Hash Table AlgorithmCollision Handling Inter-Packet Gap TimeTransmission Errors Ethernet Error-Handling ProcedureReception Errors Internal and External LoopbackReception Errors Port D Pin Functions Chapter Parallel I/O PortsSignal Function Enabling MII ModePort D Registers Shows the port D pin assignmentsCLK Sdma RegistersSdcr Field Descriptions Describes Sdcr ÞeldsFRZ Faid RAID BitsBrießy describes each enter in the FEC parameter RAM Parameter RAMFEC Parameter RAM Memory Map Address Name Description SectionRAM Perfect Match Address Low Register Addrlow RAM Hash Table High Hashtablehigh RAM Perfect Match Address High AddrhighDescribes the Addrlow Þelds Describes the Addrhigh ÞeldsDescribes Hashtablehigh Þelds RAM Hash Table Low HashtablelowHashtablehigh Field Descriptions HashhighBeginning of TxBD Ring Xdesstart Beginning of RxBD Ring RdesstartDescribes Hashtablelow Þelds Describes Rdesstart ÞeldsReceive Buffer Size Register Rbuffsize Describes Xdesstart ÞeldsXdesstart Field Descriptions Ethernet Control Register Ecntrl Spare Fecpin Etheren Reset MUXDescribes Rbuffsize Þelds Rbuffsize Field DescriptionsDescribes Ecntrl Þelds Interrupt Event IEVENT/Interrupt Mask Register ImaskEcntrl Field Descriptions FecpinmuxRfint to notify at the end of frame Ethernet Interrupt Vector Register Ivec10. IEVENT/IMASK Field Descriptions Hberr11 describes Ivec Þelds RxBD Active Register Rdesactive11. Ivec Field Descriptions IlevelTxBD Active Register Xdesactive 12 describes Rdesactive Þelds12. Rdesactive Field Descriptions MII Management Frame Register Miidata 13 describes Xdesactive Þelds13. Xdesactive Field Descriptions 14. Miidata Field Descriptions 14 describes Miidata Þelds15 describes Miispeed Þelds MII Speed Control Register Miispeed15. Miispeed Field Descriptions Dispreamble Miispeed17 describes Rbound Þelds Fifo Receive Bound Register Rbound16. Programming Examples for Miispeed Register 17. Rbound Field DescriptionsTransmit Watermark Register Xwmrk Fifo Receive Start Register Rfstart18 describes Rñfstart Þelds 18. Rfstart Field DescriptionsFifo Transmit Start Register Xfstart 19 bit Þeld descriptions for Xwmrk19. Xwmrk Field Descriptions 20 describes Xfstart Þelds DMA Function Code Register Funcode20. Xfstart Field Descriptions DATABO0 DATABO1 DESCBO0 DESCBO1 FC1 FC2 FC321 describes Funcode Þelds Receive Control Register Rcntrl21. Funcode Field Descriptions Descbo22 describes Rcntrl Þelds Receive Hash Register Rhash22. Rcntrl Field Descriptions Bcrej22 describes Rhash Þelds Transmit Control Register Xcntrl24 describes Xcntrl Þelds 23. Rhash Field DescriptionsInitialization Sequence User Initialization before Setting EcntrletherenHardware Initialization 25. Hardware InitializationDescriptor Controller Initialization 27. User Initialization before Setting EcntrletherenUser Initialization after Asserting Ecntrletheren Step DescriptionBuffer Descriptors BDs 27. User Initialization after Setting EcntrletherenEthernet Receive Buffer Descriptor RxBD Step27. Receive Buffer Descriptor RxBD Field Description RxBD format is shown in TableRO1 RO2 Data Length RO129 describes TxBD Þelds Ethernet Transmit Buffer Descriptor TxBD29. Transmit Buffer Descriptor TxBD Field Descriptions TO1 TO2 DEF CSLData Xcntrlhbc =Freescale Semiconductor, Inc AC Electrical Characteristics DC Electrical CharacteristicsMII Receive Signal Timing RXD30, RXDV, RXER, Rxclk Electrical SpeciÞcationsMII Receive Signal Timing MII Transmit Signal Timing TXD30, TXEN, TXER, TxclkMII Transmit Signal Timing Num Characteristic Min Max UnitMII Async Inputs Signal Timing MII Async Inputs Signal Timing CRS, COLTxen Txer CRS, COLMII Serial Management Channel Timing Shows the MII serial management channel timing diagramMPC860T Pin Assignments Following pins are marked as spare onFreescale Semiconductor, Inc Freescale Semiconductor, Inc For More Information On This Product