Freescale Semiconductor MPC860T MII Management Frame Register Miidata, describes Xdesactive Þelds

Page 44

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

Bits

0

1

2

3

4

5

6

7

8

9

10

11

 

12

13

14

15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Field

 

 

 

Ñ

 

 

 

X_DES_ACTIVE

 

 

 

 

Ñ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

0000_0000_0000_0000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R/W

 

 

 

 

 

 

 

Read/write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Addr

 

 

 

 

 

 

 

0xE54

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bits

16

17

18

19

20

21

22

23

24

25

26

27

 

28

29

30

31

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Field

 

 

 

 

 

 

 

Ñ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

0000_0000_0000_0000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R/W

 

 

 

 

 

 

 

Read/write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Addr

 

 

 

 

 

 

 

0xE56

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 6-12. X_DES_ACTIVE Register

Table 6-13 describes X_DES_ACTIVE Þelds.

Table 6-13. X_DES_ACTIVE Field Descriptions

Bits

Name

Description

 

 

 

0Ð6

Ñ

Reserved.

 

 

 

7

X_DES_ACTIVE

Set when this register is written, regardless of the value written. Cleared whenever no

 

 

additional ready descriptors remain in the transmit ring.

 

 

 

8Ð31

Ñ

Reserved.

 

 

 

6.2.13 MII Management Frame Register (MII_DATA)

The MII_DATA register, shown in Figure 6-13, is used to communicate with the attached MII-compatible PHY device, providing read/write access to their MII registers. Writing to MII_DATA causes a management frame to be sourced unless MII_SPEED was cleared; in this case, if MII_SPEED is then written to a non-zero value and an MII frame is generated with the data previously written to MII_DATA. This allows MII_DATA and MII_SPEED to be programmed in either order if MII_SPEED is currently zero. MII_DATA is accessed by the user and does not reset to a deÞned value.

6-12MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA

PRELIMINARYÑSUBJECTFor ore nformationTO CHANGEOn ThisWITHOUTProduct,NOTICE

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Contents
MPC860T Rev. D Fast Ethernet Controller Freescale Semiconductor, IncMotorola Literature Distribution Centers Contents Parallel I/O Ports Contents Paragraph Title Number Illustrations Title NumberViii MPC860T Rev. D Fast Ethernet Controller Supplement Tables Number Document Revision History OverviewLists signiÞcant changes between revisions of this document Document Revision HistoryFeatures Comparison with the MPC8601 MPC860TBlock Diagram Fast Ethernet Controller Embedded PowerPC Processor CoreSystem Interface Unit SIU Glueless System Design SIU Interrupt ConÞgurationInc Name Pin Description Signal DescriptionsFEC Signal Descriptions L1RSYNCB MiimdcRXD3 MiitxerREJECT3 MIITXD2REJECT4 MIITXD1Freescale Semiconductor, Inc MII Signals Signal Description FEC Signal NameTransceiver Connection This chapter discusses the operation of the FECSerial Mode Connections to the External Transceiver FEC Frame TransmissionTXD0 RXD0FEC Frame Reception Ethernet Address Recognition FEC Command SetCAM Interface Hash Table Algorithm Rcntrlprom =Inter-Packet Gap Time Collision HandlingEthernet Error-Handling Procedure Transmission ErrorsReception Errors Internal and External LoopbackReception Errors Chapter Parallel I/O Ports Port D Pin FunctionsEnabling MII Mode Signal FunctionPort D Registers Shows the port D pin assignmentsSdma Registers CLKDescribes Sdcr Þelds Sdcr Field DescriptionsFRZ Faid RAID BitsParameter RAM Brießy describes each enter in the FEC parameter RAMFEC Parameter RAM Memory Map Address Name Description SectionRAM Perfect Match Address Low Register Addrlow RAM Perfect Match Address High Addrhigh RAM Hash Table High HashtablehighDescribes the Addrlow Þelds Describes the Addrhigh ÞeldsRAM Hash Table Low Hashtablelow Describes Hashtablehigh ÞeldsHashtablehigh Field Descriptions HashhighBeginning of RxBD Ring Rdesstart Beginning of TxBD Ring XdesstartDescribes Hashtablelow Þelds Describes Rdesstart ÞeldsXdesstart Field Descriptions Receive Buffer Size Register RbuffsizeDescribes Xdesstart Þelds Spare Fecpin Etheren Reset MUX Ethernet Control Register EcntrlDescribes Rbuffsize Þelds Rbuffsize Field Descriptions Interrupt Event IEVENT/Interrupt Mask Register Imask Describes Ecntrl Þelds Ecntrl Field Descriptions FecpinmuxEthernet Interrupt Vector Register Ivec Rfint to notify at the end of frame10. IEVENT/IMASK Field Descriptions HberrRxBD Active Register Rdesactive 11 describes Ivec Þelds11. Ivec Field Descriptions Ilevel12. Rdesactive Field Descriptions TxBD Active Register Xdesactive12 describes Rdesactive Þelds 13. Xdesactive Field Descriptions MII Management Frame Register Miidata13 describes Xdesactive Þelds 14 describes Miidata Þelds 14. Miidata Field DescriptionsMII Speed Control Register Miispeed 15 describes Miispeed Þelds15. Miispeed Field Descriptions Dispreamble MiispeedFifo Receive Bound Register Rbound 17 describes Rbound Þelds16. Programming Examples for Miispeed Register 17. Rbound Field DescriptionsFifo Receive Start Register Rfstart Transmit Watermark Register Xwmrk18 describes Rñfstart Þelds 18. Rfstart Field Descriptions19. Xwmrk Field Descriptions Fifo Transmit Start Register Xfstart19 bit Þeld descriptions for Xwmrk DMA Function Code Register Funcode 20 describes Xfstart Þelds20. Xfstart Field Descriptions DATABO0 DATABO1 DESCBO0 DESCBO1 FC1 FC2 FC3Receive Control Register Rcntrl 21 describes Funcode Þelds21. Funcode Field Descriptions DescboReceive Hash Register Rhash 22 describes Rcntrl Þelds22. Rcntrl Field Descriptions BcrejTransmit Control Register Xcntrl 22 describes Rhash Þelds24 describes Xcntrl Þelds 23. Rhash Field DescriptionsUser Initialization before Setting Ecntrletheren Initialization SequenceHardware Initialization 25. Hardware Initialization27. User Initialization before Setting Ecntrletheren Descriptor Controller InitializationUser Initialization after Asserting Ecntrletheren Step Description27. User Initialization after Setting Ecntrletheren Buffer Descriptors BDsEthernet Receive Buffer Descriptor RxBD StepRxBD format is shown in Table 27. Receive Buffer Descriptor RxBD Field DescriptionRO1 RO2 Data Length RO1Ethernet Transmit Buffer Descriptor TxBD 29 describes TxBD Þelds29. Transmit Buffer Descriptor TxBD Field Descriptions TO1 TO2 DEF CSLXcntrlhbc = DataFreescale Semiconductor, Inc DC Electrical Characteristics AC Electrical CharacteristicsMII Receive Signal Timing RXD30, RXDV, RXER, Rxclk Electrical SpeciÞcationsMII Transmit Signal Timing TXD30, TXEN, TXER, Txclk MII Receive Signal TimingMII Transmit Signal Timing Num Characteristic Min Max UnitMII Async Inputs Signal Timing CRS, COL MII Async Inputs Signal TimingTxen Txer CRS, COLShows the MII serial management channel timing diagram MII Serial Management Channel TimingFollowing pins are marked as spare on MPC860T Pin AssignmentsFreescale Semiconductor, Inc Freescale Semiconductor, Inc For More Information On This Product
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