Freescale Semiconductor MPC860T user manual Tables

Page 9

Freescale Semiconductor, Inc...

Freescale Semiconductor, Inc.

TABLES

	Table	Title	Page
	Number	Title	Number
	Number		Number
	1-1	Document Revision History	1-1
	2-1	FEC Signal Descriptions	2-1
	3-1	MII Signals	3-1
	3-2	Serial Mode Connections to the External Transceiver	3-2
	3-3	Transmission Errors	3-7
	3-4	Reception Errors	3-8
	4-1	Port D Pin Assignment	4-2
	5-1	SDCR Field Descriptions	5-2
	6-1	FEC Parameter RAM Memory Map	6-1
	6-2	ADDR_LOW Field Descriptions	6-3
	6-3	ADDR_HIGH Field Descriptions	6-3
	6-4	HASH_TABLE_HIGH Field Descriptions	6-4
	6-5	HASH_TABLE_LOW Field Descriptions	6-5
	6-6	R_DES_START Field Descriptions	6-5
	6-7	X_DES_START Field Descriptions	6-6
	6-8	R_BUFF_SIZE Field Descriptions	6-7
	6-9	ECNTRL Field Descriptions	6-8
	6-10	I_EVENT/I_MASK Field Descriptions	6-9
	6-11	IVEC Field Descriptions	6-10
	6-12	R_DES_ACTIVE Field Descriptions	6-11
	6-13	X_DES_ACTIVE Field Descriptions	6-12
	6-14	MII_DATA Field Descriptions	6-13
	6-15	MII_SPEED Field Descriptions	6-14
	6-16	Programming Examples for MII_SPEED Register	6-15
	6-17	R_BOUND Field Descriptions	6-15
	6-18	R_FSTART Field Descriptions	6-16
	6-19	X_WMRK Field Descriptions	6-17
	6-20	X_FSTART Field Descriptions	6-18
	6-21	FUN_CODE Field Descriptions	6-19
	6-22	R_CNTRL Field Descriptions	6-20
	6-23	R_HASH Field Descriptions	6-21
	6-24	X_CNTRL Field Descriptions	6-21
	6-25	Hardware Initialization	6-22
	6-26	ECNTRL[ETHER_EN] Deassertion Initialization	6-22
	6-27	User Initialization (before Setting ECNTRL[ETHER_EN])	6-23
	6-27	User Initialization (after Setting ECNTRL[ETHER_EN])	6-24

	MOTOROLA	Tables	ix
		PRELIMINARYÑSUBJECTFor ore nformation On This Product,
		TO CHANGE WITHOUT NOTICE

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Contents Freescale Semiconductor, Inc MPC860T Rev. D Fast Ethernet ControllerMotorola Literature Distribution Centers Contents Parallel I/O Ports Contents Paragraph Title Number Title Number IllustrationsViii MPC860T Rev. D Fast Ethernet Controller Supplement Tables Number Overview Document Revision HistoryLists signiÞcant changes between revisions of this document Document Revision HistoryComparison with the MPC860 Features1 MPC860TBlock Diagram Embedded PowerPC Processor Core System Interface Unit SIUFast Ethernet Controller SIU Interrupt ConÞguration Glueless System DesignInc Signal Descriptions FEC Signal DescriptionsName Pin Description Miimdc L1RSYNCBRXD3 MiitxerMIITXD2 REJECT3REJECT4 MIITXD1Freescale Semiconductor, Inc Signal Description FEC Signal Name MII SignalsTransceiver Connection This chapter discusses the operation of the FECFEC Frame Transmission Serial Mode Connections to the External TransceiverTXD0 RXD0FEC Frame Reception FEC Command Set CAM InterfaceEthernet Address Recognition Rcntrlprom = Hash Table AlgorithmCollision Handling Inter-Packet Gap TimeTransmission Errors Ethernet Error-Handling ProcedureReception Errors Internal and External LoopbackReception Errors Port D Pin Functions Chapter Parallel I/O PortsSignal Function Enabling MII ModePort D Registers Shows the port D pin assignmentsCLK Sdma RegistersSdcr Field Descriptions Describes Sdcr ÞeldsFRZ Faid RAID BitsBrießy describes each enter in the FEC parameter RAM Parameter RAMFEC Parameter RAM Memory Map Address Name Description SectionRAM Perfect Match Address Low Register Addrlow RAM Hash Table High Hashtablehigh RAM Perfect Match Address High AddrhighDescribes the Addrlow Þelds Describes the Addrhigh ÞeldsDescribes Hashtablehigh Þelds RAM Hash Table Low HashtablelowHashtablehigh Field Descriptions HashhighBeginning of TxBD Ring Xdesstart Beginning of RxBD Ring RdesstartDescribes Hashtablelow Þelds Describes Rdesstart ÞeldsReceive Buffer Size Register Rbuffsize Describes Xdesstart ÞeldsXdesstart Field Descriptions Ethernet Control Register Ecntrl Spare Fecpin Etheren Reset MUXDescribes Rbuffsize Þelds Rbuffsize Field DescriptionsDescribes Ecntrl Þelds Interrupt Event IEVENT/Interrupt Mask Register ImaskEcntrl Field Descriptions FecpinmuxRfint to notify at the end of frame Ethernet Interrupt Vector Register Ivec10. IEVENT/IMASK Field Descriptions Hberr11 describes Ivec Þelds RxBD Active Register Rdesactive11. Ivec Field Descriptions IlevelTxBD Active Register Xdesactive 12 describes Rdesactive Þelds12. Rdesactive Field Descriptions MII Management Frame Register Miidata 13 describes Xdesactive Þelds13. Xdesactive Field Descriptions 14. Miidata Field Descriptions 14 describes Miidata Þelds15 describes Miispeed Þelds MII Speed Control Register Miispeed15. Miispeed Field Descriptions Dispreamble Miispeed17 describes Rbound Þelds Fifo Receive Bound Register Rbound16. Programming Examples for Miispeed Register 17. Rbound Field DescriptionsTransmit Watermark Register Xwmrk Fifo Receive Start Register Rfstart18 describes Rñfstart Þelds 18. Rfstart Field DescriptionsFifo Transmit Start Register Xfstart 19 bit Þeld descriptions for Xwmrk19. Xwmrk Field Descriptions 20 describes Xfstart Þelds DMA Function Code Register Funcode20. Xfstart Field Descriptions DATABO0 DATABO1 DESCBO0 DESCBO1 FC1 FC2 FC321 describes Funcode Þelds Receive Control Register Rcntrl21. Funcode Field Descriptions Descbo22 describes Rcntrl Þelds Receive Hash Register Rhash22. Rcntrl Field Descriptions Bcrej22 describes Rhash Þelds Transmit Control Register Xcntrl24 describes Xcntrl Þelds 23. Rhash Field DescriptionsInitialization Sequence User Initialization before Setting EcntrletherenHardware Initialization 25. Hardware InitializationDescriptor Controller Initialization 27. User Initialization before Setting EcntrletherenUser Initialization after Asserting Ecntrletheren Step DescriptionBuffer Descriptors BDs 27. User Initialization after Setting EcntrletherenEthernet Receive Buffer Descriptor RxBD Step27. Receive Buffer Descriptor RxBD Field Description RxBD format is shown in TableRO1 RO2 Data Length RO129 describes TxBD Þelds Ethernet Transmit Buffer Descriptor TxBD29. Transmit Buffer Descriptor TxBD Field Descriptions TO1 TO2 DEF CSLData Xcntrlhbc =Freescale Semiconductor, Inc AC Electrical Characteristics DC Electrical CharacteristicsMII Receive Signal Timing RXD30, RXDV, RXER, Rxclk Electrical SpeciÞcationsMII Receive Signal Timing MII Transmit Signal Timing TXD30, TXEN, TXER, TxclkMII Transmit Signal Timing Num Characteristic Min Max UnitMII Async Inputs Signal Timing MII Async Inputs Signal Timing CRS, COLTxen Txer CRS, COLMII Serial Management Channel Timing Shows the MII serial management channel timing diagramMPC860T Pin Assignments Following pins are marked as spare onFreescale Semiconductor, Inc Freescale Semiconductor, Inc For More Information On This Product