Freescale Semiconductor MPC860T user manual Inter-Packet Gap Time, Collision Handling

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Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

of the CRC-encoded result to generate a number between 0 and 63.

Bit 31 of the CRC result selects HASH_TABLE_HIGH (bit 31 = 1) or HASH_TABLE_LOW (bit 31 = 0). Bits 30Ð26 of the CRC result select the bit in the selected register. If that bit is set in the hash table, the frame is accepted; otherwise, it is rejected. The result is that if eight group addresses are stored in the hash table and random group addresses are received, the hash table prevents roughly 56/64 (or 87.5%) of the group address frames from reaching memory. The processor must further Þlter those that reach memory to determine if they truly contain one of the eight preferred addresses.

The effectiveness of the hash table declines as the number of addresses increases.

The user must initialize the hash table registers. The FEC does not support the SET GROUP ADDRESS command, which can be used in CPM ethernet controllers. The user may compute the hash for a particular address in software or use the SET GROUP ADDRESS command in an off-line CPM channel, retrieve the result, and use it to program the FEC hash table registers. The CRC32 polynomial to use in computing the hash is as follows:

X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1

3.8 Inter-Packet Gap Time

The minimum inter-packet gap time for back-to-back transmission is 96 bit times. After completing a transmission or after the backoff algorithm completes, the transmitter waits for the carrier sense signal (CRS) to be negated before starting its 96 bit time IPG counter. Frame transmission may begin 96 bit times after CRS is negated if it stays negated for at least 60 bit times. If CRS asserts during the last 36 bit times it is ignored and a collision occurs.

The receiver receives back-to-back frames with a minimum spacing of at least 28 bit times. If an interrupted gap between receive frames is less than 28 bit times, the receiver may discard the next frame.

3.9 Collision Handling

If a collision occurs during frame transmission, the FEC continues transmitting for at least 32 bit times, sending a JAM pattern of 32 ones. If the collision occurs during the preamble sequence, the JAM pattern is sent after the preamble sequence.

If a collision occurs within 64 byte times, the retry process is initiated. The transmitter waits a random number of slot times. A slot time is 512 bit times. If a collision occurs after 64 byte times, no retransmission is performed and the end of frame buffer is closed with an LC error indication.

3-6MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA

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Contents MPC860T Rev. D Fast Ethernet Controller Freescale Semiconductor, IncMotorola Literature Distribution Centers Contents Parallel I/O Ports Contents Paragraph Title Number Illustrations Title NumberViii MPC860T Rev. D Fast Ethernet Controller Supplement Tables Number Lists signiÞcant changes between revisions of this document Document Revision HistoryOverview Document Revision HistoryFeatures Comparison with the MPC8601 MPC860TBlock Diagram Fast Ethernet Controller Embedded PowerPC Processor CoreSystem Interface Unit SIU Glueless System Design SIU Interrupt ConÞgurationInc Name Pin Description Signal DescriptionsFEC Signal Descriptions RXD3 L1RSYNCBMiimdc MiitxerREJECT4 REJECT3MIITXD2 MIITXD1Freescale Semiconductor, Inc Transceiver Connection MII SignalsSignal Description FEC Signal Name This chapter discusses the operation of the FECTXD0 Serial Mode Connections to the External TransceiverFEC Frame Transmission RXD0FEC Frame Reception Ethernet Address Recognition FEC Command SetCAM Interface Hash Table Algorithm Rcntrlprom =Inter-Packet Gap Time Collision HandlingReception Errors Ethernet Error-Handling ProcedureTransmission Errors Internal and External LoopbackReception Errors Chapter Parallel I/O Ports Port D Pin FunctionsPort D Registers Enabling MII ModeSignal Function Shows the port D pin assignmentsSdma Registers CLKFRZ Faid RAID Describes Sdcr ÞeldsSdcr Field Descriptions BitsFEC Parameter RAM Memory Map Parameter RAMBrießy describes each enter in the FEC parameter RAM Address Name Description SectionRAM Perfect Match Address Low Register Addrlow Describes the Addrlow Þelds RAM Perfect Match Address High AddrhighRAM Hash Table High Hashtablehigh Describes the Addrhigh ÞeldsHashtablehigh Field Descriptions RAM Hash Table Low HashtablelowDescribes Hashtablehigh Þelds HashhighDescribes Hashtablelow Þelds Beginning of RxBD Ring RdesstartBeginning of TxBD Ring Xdesstart Describes Rdesstart ÞeldsXdesstart Field Descriptions Receive Buffer Size Register RbuffsizeDescribes Xdesstart Þelds Describes Rbuffsize Þelds Spare Fecpin Etheren Reset MUXEthernet Control Register Ecntrl Rbuffsize Field DescriptionsEcntrl Field Descriptions Interrupt Event IEVENT/Interrupt Mask Register ImaskDescribes Ecntrl Þelds Fecpinmux10. IEVENT/IMASK Field Descriptions Ethernet Interrupt Vector Register IvecRfint to notify at the end of frame Hberr11. Ivec Field Descriptions RxBD Active Register Rdesactive11 describes Ivec Þelds Ilevel12. Rdesactive Field Descriptions TxBD Active Register Xdesactive12 describes Rdesactive Þelds 13. Xdesactive Field Descriptions MII Management Frame Register Miidata13 describes Xdesactive Þelds 14 describes Miidata Þelds 14. Miidata Field Descriptions15. Miispeed Field Descriptions MII Speed Control Register Miispeed15 describes Miispeed Þelds Dispreamble Miispeed16. Programming Examples for Miispeed Register Fifo Receive Bound Register Rbound17 describes Rbound Þelds 17. Rbound Field Descriptions18 describes Rñfstart Þelds Fifo Receive Start Register RfstartTransmit Watermark Register Xwmrk 18. Rfstart Field Descriptions19. Xwmrk Field Descriptions Fifo Transmit Start Register Xfstart19 bit Þeld descriptions for Xwmrk 20. Xfstart Field Descriptions DMA Function Code Register Funcode20 describes Xfstart Þelds DATABO0 DATABO1 DESCBO0 DESCBO1 FC1 FC2 FC321. Funcode Field Descriptions Receive Control Register Rcntrl21 describes Funcode Þelds Descbo22. Rcntrl Field Descriptions Receive Hash Register Rhash22 describes Rcntrl Þelds Bcrej24 describes Xcntrl Þelds Transmit Control Register Xcntrl22 describes Rhash Þelds 23. Rhash Field DescriptionsHardware Initialization User Initialization before Setting EcntrletherenInitialization Sequence 25. Hardware InitializationUser Initialization after Asserting Ecntrletheren 27. User Initialization before Setting EcntrletherenDescriptor Controller Initialization Step DescriptionEthernet Receive Buffer Descriptor RxBD 27. User Initialization after Setting EcntrletherenBuffer Descriptors BDs StepRO1 RO2 Data Length RxBD format is shown in Table27. Receive Buffer Descriptor RxBD Field Description RO129. Transmit Buffer Descriptor TxBD Field Descriptions Ethernet Transmit Buffer Descriptor TxBD29 describes TxBD Þelds TO1 TO2 DEF CSLXcntrlhbc = DataFreescale Semiconductor, Inc MII Receive Signal Timing RXD30, RXDV, RXER, Rxclk DC Electrical CharacteristicsAC Electrical Characteristics Electrical SpeciÞcationsMII Transmit Signal Timing MII Transmit Signal Timing TXD30, TXEN, TXER, TxclkMII Receive Signal Timing Num Characteristic Min Max UnitTxen Txer MII Async Inputs Signal Timing CRS, COLMII Async Inputs Signal Timing CRS, COLShows the MII serial management channel timing diagram MII Serial Management Channel TimingFollowing pins are marked as spare on MPC860T Pin AssignmentsFreescale Semiconductor, Inc Freescale Semiconductor, Inc For More Information On This Product
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