Freescale Semiconductor MPC860T user manual Ethernet Interrupt Vector Register Ivec, Hberr

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Freescale Semiconductor, Inc.

 

 

Freescale Semiconductor, Inc.

and RFINT to notify at the end of frame.

 

 

Table 6-10. I_EVENT/I_MASK Field Descriptions

 

 

 

Bits

Name

Description

 

 

 

0

HBERR

Heartbeat error. When I_EVENT[HBC] is set, this interrupt indicates that heartbeat was not

 

 

detected within the heartbeat window following a transmission.

 

 

 

1

BABR

Babbling receive error. Indicates a received frame exceeded MAX_FRAME_LENGTH bytes. The

 

 

hardware truncates receive frames exceeding 2047 bytes so as not to overßow receive buffers.

 

 

Note that the Þrst revision of the MPC860T (mask #H56S) must not be given frames in excess of

 

 

2047 as it does not truncate frames.

 

 

 

2

BABT

Babbling transmit error. Indicates that the transmitted frame exceeded MAX_FRAME_LENGTH

 

 

bytes. This condition is usually caused by too large a a frame being placed into the transmit data

 

 

buffers. The transmit frame is not truncated.

 

 

 

3

GRA

Graceful stop complete. A graceful stop initiated by the setting of GTS is complete. GRA is set

 

 

when the transmitter Þnishes sending any frame that was in progress when GTS was set.

 

 

 

4

TFINT

Transmit frame interrupt. Indicates that a frame was sent and that the last corresponding BD was

 

 

updated.

 

 

 

5

TXB

Transmit buffer interrupt. Indicates that a TxBD was updated.

 

 

 

6

RFINT

Receive frame interrupt. Indicates that a frame was received and that the last corresponding BD

 

 

was updated.

 

 

 

7

RXB

Receive buffer interrupt. Indicates that a RxBD was updated.

 

 

 

8

MII

MII interrupt. Indicates that the MII completed the requested data transfer.

 

 

 

9

EBERR

Ethernet bus error occurred. Indicates that a bus error occurred when the FEC was accessing the

 

 

U bus.

 

 

 

10Ð31

Ñ

Reserved. Should written to zero by the host processor.

 

 

 

6.2.10 Ethernet Interrupt Vector Register (IVEC)

The Ethernet interrupt vector register (IVEC), shown in Table 6-11, indicates the class of interrupt generated by the FEC (IVEC) and provides control of the interrupt level (ILEVEL).

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Contents Freescale Semiconductor, Inc MPC860T Rev. D Fast Ethernet ControllerMotorola Literature Distribution Centers Contents Parallel I/O Ports Contents Paragraph Title Number Title Number IllustrationsViii MPC860T Rev. D Fast Ethernet Controller Supplement Tables Number Overview Document Revision HistoryLists signiÞcant changes between revisions of this document Document Revision HistoryComparison with the MPC860 Features1 MPC860TBlock Diagram Fast Ethernet Controller Embedded PowerPC Processor CoreSystem Interface Unit SIU SIU Interrupt ConÞguration Glueless System DesignInc Name Pin Description Signal DescriptionsFEC Signal Descriptions Miimdc L1RSYNCBRXD3 MiitxerMIITXD2 REJECT3REJECT4 MIITXD1Freescale Semiconductor, Inc Signal Description FEC Signal Name MII SignalsTransceiver Connection This chapter discusses the operation of the FECFEC Frame Transmission Serial Mode Connections to the External TransceiverTXD0 RXD0FEC Frame Reception Ethernet Address Recognition FEC Command SetCAM Interface Rcntrlprom = Hash Table AlgorithmCollision Handling Inter-Packet Gap TimeTransmission Errors Ethernet Error-Handling ProcedureReception Errors Internal and External LoopbackReception Errors Port D Pin Functions Chapter Parallel I/O PortsSignal Function Enabling MII ModePort D Registers Shows the port D pin assignmentsCLK Sdma RegistersSdcr Field Descriptions Describes Sdcr ÞeldsFRZ Faid RAID BitsBrießy describes each enter in the FEC parameter RAM Parameter RAMFEC Parameter RAM Memory Map Address Name Description SectionRAM Perfect Match Address Low Register Addrlow RAM Hash Table High Hashtablehigh RAM Perfect Match Address High AddrhighDescribes the Addrlow Þelds Describes the Addrhigh ÞeldsDescribes Hashtablehigh Þelds RAM Hash Table Low HashtablelowHashtablehigh Field Descriptions HashhighBeginning of TxBD Ring Xdesstart Beginning of RxBD Ring RdesstartDescribes Hashtablelow Þelds Describes Rdesstart ÞeldsXdesstart Field Descriptions Receive Buffer Size Register RbuffsizeDescribes Xdesstart Þelds Ethernet Control Register Ecntrl Spare Fecpin Etheren Reset MUXDescribes Rbuffsize Þelds Rbuffsize Field DescriptionsDescribes Ecntrl Þelds Interrupt Event IEVENT/Interrupt Mask Register ImaskEcntrl Field Descriptions FecpinmuxRfint to notify at the end of frame Ethernet Interrupt Vector Register Ivec10. IEVENT/IMASK Field Descriptions Hberr11 describes Ivec Þelds RxBD Active Register Rdesactive11. Ivec Field Descriptions Ilevel12. Rdesactive Field Descriptions TxBD Active Register Xdesactive12 describes Rdesactive Þelds 13. Xdesactive Field Descriptions MII Management Frame Register Miidata13 describes Xdesactive Þelds 14. Miidata Field Descriptions 14 describes Miidata Þelds15 describes Miispeed Þelds MII Speed Control Register Miispeed15. Miispeed Field Descriptions Dispreamble Miispeed17 describes Rbound Þelds Fifo Receive Bound Register Rbound16. Programming Examples for Miispeed Register 17. Rbound Field DescriptionsTransmit Watermark Register Xwmrk Fifo Receive Start Register Rfstart18 describes Rñfstart Þelds 18. Rfstart Field Descriptions19. Xwmrk Field Descriptions Fifo Transmit Start Register Xfstart19 bit Þeld descriptions for Xwmrk 20 describes Xfstart Þelds DMA Function Code Register Funcode20. Xfstart Field Descriptions DATABO0 DATABO1 DESCBO0 DESCBO1 FC1 FC2 FC321 describes Funcode Þelds Receive Control Register Rcntrl21. Funcode Field Descriptions Descbo22 describes Rcntrl Þelds Receive Hash Register Rhash22. Rcntrl Field Descriptions Bcrej22 describes Rhash Þelds Transmit Control Register Xcntrl24 describes Xcntrl Þelds 23. Rhash Field DescriptionsInitialization Sequence User Initialization before Setting EcntrletherenHardware Initialization 25. Hardware InitializationDescriptor Controller Initialization 27. User Initialization before Setting EcntrletherenUser Initialization after Asserting Ecntrletheren Step DescriptionBuffer Descriptors BDs 27. User Initialization after Setting EcntrletherenEthernet Receive Buffer Descriptor RxBD Step27. Receive Buffer Descriptor RxBD Field Description RxBD format is shown in TableRO1 RO2 Data Length RO129 describes TxBD Þelds Ethernet Transmit Buffer Descriptor TxBD29. Transmit Buffer Descriptor TxBD Field Descriptions TO1 TO2 DEF CSLData Xcntrlhbc =Freescale Semiconductor, Inc AC Electrical Characteristics DC Electrical CharacteristicsMII Receive Signal Timing RXD30, RXDV, RXER, Rxclk Electrical SpeciÞcationsMII Receive Signal Timing MII Transmit Signal Timing TXD30, TXEN, TXER, TxclkMII Transmit Signal Timing Num Characteristic Min Max UnitMII Async Inputs Signal Timing MII Async Inputs Signal Timing CRS, COLTxen Txer CRS, COLMII Serial Management Channel Timing Shows the MII serial management channel timing diagramMPC860T Pin Assignments Following pins are marked as spare onFreescale Semiconductor, Inc Freescale Semiconductor, Inc For More Information On This Product
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