Freescale Semiconductor MPC860T CAM Interface, FEC Command Set, Ethernet Address Recognition

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Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

of the frame to the associated data buffer.

R_BUFF_SIZE[R_BUFF_SIZE] determines buffer length, which should be at least 128 bytes. R_BUFF_SIZE must be quad-word (16-byte) aligned.

During reception, the FEC checks for a frame that is either too short or too long. When the frame ends (CRS is negated), the receive CRC Þeld is checked and written to the data buffer. The data length written to the last BD in the Ethernet frame is the length of the entire frame. Frames smaller than 64 bytes are not accessed and are rejected in hardware with no impact on system bus usage.

Receive frames are not truncated if they exceed MAX_FRAME_LENGTH bytes, however the babbling receive error interrupt occurs (I_EVENT[BABR] = 1) and RxBD[LG] is set.

When the receive frame is complete, the FEC sets RxBD[L], writes the other frame status bits into the RxBD, and clears the E bit. The FEC next generates a maskable interrupt (I_EVENT[RFINT] maskable by I_MASK[RFIEN]), indicating that a frame has been received and is in memory. The FEC then waits for a new frame.

The FEC receives serial data lsb Þrst.

3.4 CAM Interface

In addition to the FEC address recognition logic, an external CAM may be used for frame reject with no additional pins other than the MII interface pins. For more information on the CAM interface refer to Using MotorolaÕs Fast Static RAM CAMs with the MPC860TÕs Media Independent Interface application note.

3.5 FEC Command Set

The FEC does not support commands as found in the CPM channels. After the FEC is initialized and enabled, it operates autonomously. Typically, aside from initialization, the driver only writes to R_DES_ACTIVE, X_DES_ACTIVE, and I_EVENT during operation.

3.6 Ethernet Address Recognition

The FEC Þlters the received frames based on destination address (DA) typeÑindividual (unicast), group (multicast), or broadcast (all-ones group address). The difference between an individual address and a group address is determined by the I/G bit in the destination address Þeld. Figure 3-1 shows a ßowchart for address recognition on received frames.

If the DA is the individual (unicast) type of address, the FEC compares the destination address Þeld of the received frame with the 48-bit address that the user programs in the ADDR_LOW and ADDR_HIGH.

If the DA is the group type of address, the FEC determines whether the group address is a

3-4MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA

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Contents
MPC860T Rev. D Fast Ethernet Controller Freescale Semiconductor, IncMotorola Literature Distribution Centers Contents Parallel I/O Ports Contents Paragraph Title Number Illustrations Title NumberViii MPC860T Rev. D Fast Ethernet Controller Supplement Tables Number Document Revision History OverviewLists signiÞcant changes between revisions of this document Document Revision HistoryFeatures Comparison with the MPC8601 MPC860TBlock Diagram Embedded PowerPC Processor Core System Interface Unit SIUFast Ethernet Controller Glueless System Design SIU Interrupt ConÞgurationInc Signal Descriptions FEC Signal DescriptionsName Pin Description L1RSYNCB MiimdcRXD3 MiitxerREJECT3 MIITXD2REJECT4 MIITXD1 Freescale Semiconductor, Inc MII Signals Signal Description FEC Signal NameTransceiver Connection This chapter discusses the operation of the FECSerial Mode Connections to the External Transceiver FEC Frame TransmissionTXD0 RXD0FEC Frame Reception FEC Command Set CAM InterfaceEthernet Address Recognition Hash Table Algorithm Rcntrlprom =Inter-Packet Gap Time Collision HandlingEthernet Error-Handling Procedure Transmission ErrorsReception Errors Internal and External LoopbackReception Errors Chapter Parallel I/O Ports Port D Pin FunctionsEnabling MII Mode Signal FunctionPort D Registers Shows the port D pin assignmentsSdma Registers CLKDescribes Sdcr Þelds Sdcr Field DescriptionsFRZ Faid RAID BitsParameter RAM Brießy describes each enter in the FEC parameter RAMFEC Parameter RAM Memory Map Address Name Description SectionRAM Perfect Match Address Low Register Addrlow RAM Perfect Match Address High Addrhigh RAM Hash Table High HashtablehighDescribes the Addrlow Þelds Describes the Addrhigh ÞeldsRAM Hash Table Low Hashtablelow Describes Hashtablehigh ÞeldsHashtablehigh Field Descriptions HashhighBeginning of RxBD Ring Rdesstart Beginning of TxBD Ring XdesstartDescribes Hashtablelow Þelds Describes Rdesstart ÞeldsReceive Buffer Size Register Rbuffsize Describes Xdesstart ÞeldsXdesstart Field Descriptions Spare Fecpin Etheren Reset MUX Ethernet Control Register EcntrlDescribes Rbuffsize Þelds Rbuffsize Field DescriptionsInterrupt Event IEVENT/Interrupt Mask Register Imask Describes Ecntrl ÞeldsEcntrl Field Descriptions FecpinmuxEthernet Interrupt Vector Register Ivec Rfint to notify at the end of frame10. IEVENT/IMASK Field Descriptions HberrRxBD Active Register Rdesactive 11 describes Ivec Þelds11. Ivec Field Descriptions IlevelTxBD Active Register Xdesactive 12 describes Rdesactive Þelds12. Rdesactive Field Descriptions MII Management Frame Register Miidata 13 describes Xdesactive Þelds13. Xdesactive Field Descriptions 14 describes Miidata Þelds 14. Miidata Field DescriptionsMII Speed Control Register Miispeed 15 describes Miispeed Þelds15. Miispeed Field Descriptions Dispreamble MiispeedFifo Receive Bound Register Rbound 17 describes Rbound Þelds16. Programming Examples for Miispeed Register 17. Rbound Field DescriptionsFifo Receive Start Register Rfstart Transmit Watermark Register Xwmrk18 describes Rñfstart Þelds 18. Rfstart Field DescriptionsFifo Transmit Start Register Xfstart 19 bit Þeld descriptions for Xwmrk19. Xwmrk Field Descriptions DMA Function Code Register Funcode 20 describes Xfstart Þelds20. Xfstart Field Descriptions DATABO0 DATABO1 DESCBO0 DESCBO1 FC1 FC2 FC3Receive Control Register Rcntrl 21 describes Funcode Þelds21. Funcode Field Descriptions DescboReceive Hash Register Rhash 22 describes Rcntrl Þelds22. Rcntrl Field Descriptions BcrejTransmit Control Register Xcntrl 22 describes Rhash Þelds24 describes Xcntrl Þelds 23. Rhash Field DescriptionsUser Initialization before Setting Ecntrletheren Initialization SequenceHardware Initialization 25. Hardware Initialization27. User Initialization before Setting Ecntrletheren Descriptor Controller InitializationUser Initialization after Asserting Ecntrletheren Step Description27. User Initialization after Setting Ecntrletheren Buffer Descriptors BDsEthernet Receive Buffer Descriptor RxBD StepRxBD format is shown in Table 27. Receive Buffer Descriptor RxBD Field DescriptionRO1 RO2 Data Length RO1Ethernet Transmit Buffer Descriptor TxBD 29 describes TxBD Þelds29. Transmit Buffer Descriptor TxBD Field Descriptions TO1 TO2 DEF CSLXcntrlhbc = DataFreescale Semiconductor, Inc DC Electrical Characteristics AC Electrical CharacteristicsMII Receive Signal Timing RXD30, RXDV, RXER, Rxclk Electrical SpeciÞcationsMII Transmit Signal Timing TXD30, TXEN, TXER, Txclk MII Receive Signal TimingMII Transmit Signal Timing Num Characteristic Min Max UnitMII Async Inputs Signal Timing CRS, COL MII Async Inputs Signal TimingTxen Txer CRS, COLShows the MII serial management channel timing diagram MII Serial Management Channel TimingFollowing pins are marked as spare on MPC860T Pin AssignmentsFreescale Semiconductor, Inc Freescale Semiconductor, Inc For More Information On This Product
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