Freescale Semiconductor MPC860T Buffer Descriptors BDs, Ethernet Receive Buffer Descriptor RxBD

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Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

(though these steps could also be done before setting ETHER_EN).

Table 6-27. User Initialization (after Setting ECNTRL[ETHER_EN])

Step

Description

1Fill RxBD ring with empty buffers

2 Set R_DES_ACTIVE

6.4Buffer Descriptors (BDs)

Data for Fast Ethernet frames must reside in memory external to the MPC860T device. Frame data is placed in one or more buffers, each of which is pointed to by a BD, which also contains the current state of the buffer. For maximum user ßexibility, BDs are also located in external memory.

A buffer is produced by setting TxBD[R] or RxBD[E]. Writing to either X_DES_ACTIVE or R_DES_ACTIVE indicates that a buffer is in external memory for the transmit or receive data trafÞc, respectively. The hardware reads the BDs and processes the buffers. After the data DMA completes and the BD status bits are written by the DMA engine, hardware clears TxBD[R] or RxBD[E] to signal that the buffer was processed. Software can poll the BDs or may rely on the buffer/frame interrupts to detect when buffers have been processed.

ECNTRL[ETHER_EN] operates as a reset to the BD/DMA logic. When ETHER_EN is cleared, the DMA engine BD pointers are reset to point to the starting TxBDs and RxBDs. The BDs are not initialized by hardware during reset. At least one TxBD and one RxBD must be initialized by software (write 0x0000_0000 to the most signiÞcant word of the BD) before ETHER_EN is set.

The BDs operate as a ring. R_DES_START deÞnes the starting address for the RxBD ring and X_DES_START deÞnes the starting address for TxBD ring. The last BD in each ring is indicated by the wrap (W) bit. When set, W indicates that the next BD in the ring is at the location pointed to by R_DES_START and X_DES_START for the receive and transmit rings, respectively. BD rings must start on a double-word boundary.

6.4.1 Ethernet Receive Buffer Descriptor (RxBD)

The RxBD is shown in Figure 6-23. The Þrst word of the RxBD contains control and status bits. The user initializes RxBD[E,W] and the Rx buffer pointer. When the buffer has been accessed by a DMA, the FEC modiÞes RxBD[E,L,M,BC,MC,LG,NO,SH,CR,OV,TR] and writes the length of the used portion of the buffer in the Þrst word. The FEC modiÞes RxBD[M,BC,MC,LG,NO,SH,CR,TR,OV] only if L = 1.

6-24MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA

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Contents MPC860T Rev. D Fast Ethernet Controller Freescale Semiconductor, IncMotorola Literature Distribution Centers Contents Parallel I/O Ports Contents Paragraph Title Number Illustrations Title NumberViii MPC860T Rev. D Fast Ethernet Controller Supplement Tables Number Document Revision History OverviewLists signiÞcant changes between revisions of this document Document Revision HistoryFeatures Comparison with the MPC8601 MPC860TBlock Diagram Fast Ethernet Controller Embedded PowerPC Processor CoreSystem Interface Unit SIU Glueless System Design SIU Interrupt ConÞgurationInc Name Pin Description Signal DescriptionsFEC Signal Descriptions L1RSYNCB MiimdcRXD3 MiitxerREJECT3 MIITXD2REJECT4 MIITXD1Freescale Semiconductor, Inc MII Signals Signal Description FEC Signal NameTransceiver Connection This chapter discusses the operation of the FECSerial Mode Connections to the External Transceiver FEC Frame TransmissionTXD0 RXD0FEC Frame Reception Ethernet Address Recognition FEC Command SetCAM Interface Hash Table Algorithm Rcntrlprom =Inter-Packet Gap Time Collision HandlingEthernet Error-Handling Procedure Transmission ErrorsReception Errors Internal and External LoopbackReception Errors Chapter Parallel I/O Ports Port D Pin FunctionsEnabling MII Mode Signal FunctionPort D Registers Shows the port D pin assignmentsSdma Registers CLKDescribes Sdcr Þelds Sdcr Field DescriptionsFRZ Faid RAID BitsParameter RAM Brießy describes each enter in the FEC parameter RAMFEC Parameter RAM Memory Map Address Name Description SectionRAM Perfect Match Address Low Register Addrlow RAM Perfect Match Address High Addrhigh RAM Hash Table High HashtablehighDescribes the Addrlow Þelds Describes the Addrhigh ÞeldsRAM Hash Table Low Hashtablelow Describes Hashtablehigh ÞeldsHashtablehigh Field Descriptions HashhighBeginning of RxBD Ring Rdesstart Beginning of TxBD Ring XdesstartDescribes Hashtablelow Þelds Describes Rdesstart ÞeldsXdesstart Field Descriptions Receive Buffer Size Register RbuffsizeDescribes Xdesstart Þelds Spare Fecpin Etheren Reset MUX Ethernet Control Register EcntrlDescribes Rbuffsize Þelds Rbuffsize Field DescriptionsInterrupt Event IEVENT/Interrupt Mask Register Imask Describes Ecntrl ÞeldsEcntrl Field Descriptions FecpinmuxEthernet Interrupt Vector Register Ivec Rfint to notify at the end of frame10. IEVENT/IMASK Field Descriptions HberrRxBD Active Register Rdesactive 11 describes Ivec Þelds11. Ivec Field Descriptions Ilevel12. Rdesactive Field Descriptions TxBD Active Register Xdesactive12 describes Rdesactive Þelds 13. Xdesactive Field Descriptions MII Management Frame Register Miidata13 describes Xdesactive Þelds 14 describes Miidata Þelds 14. Miidata Field DescriptionsMII Speed Control Register Miispeed 15 describes Miispeed Þelds15. Miispeed Field Descriptions Dispreamble MiispeedFifo Receive Bound Register Rbound 17 describes Rbound Þelds16. Programming Examples for Miispeed Register 17. Rbound Field DescriptionsFifo Receive Start Register Rfstart Transmit Watermark Register Xwmrk18 describes Rñfstart Þelds 18. Rfstart Field Descriptions19. Xwmrk Field Descriptions Fifo Transmit Start Register Xfstart19 bit Þeld descriptions for Xwmrk DMA Function Code Register Funcode 20 describes Xfstart Þelds20. Xfstart Field Descriptions DATABO0 DATABO1 DESCBO0 DESCBO1 FC1 FC2 FC3Receive Control Register Rcntrl 21 describes Funcode Þelds21. Funcode Field Descriptions DescboReceive Hash Register Rhash 22 describes Rcntrl Þelds22. Rcntrl Field Descriptions BcrejTransmit Control Register Xcntrl 22 describes Rhash Þelds24 describes Xcntrl Þelds 23. Rhash Field DescriptionsUser Initialization before Setting Ecntrletheren Initialization SequenceHardware Initialization 25. Hardware Initialization27. User Initialization before Setting Ecntrletheren Descriptor Controller InitializationUser Initialization after Asserting Ecntrletheren Step Description27. User Initialization after Setting Ecntrletheren Buffer Descriptors BDsEthernet Receive Buffer Descriptor RxBD StepRxBD format is shown in Table 27. Receive Buffer Descriptor RxBD Field DescriptionRO1 RO2 Data Length RO1Ethernet Transmit Buffer Descriptor TxBD 29 describes TxBD Þelds29. Transmit Buffer Descriptor TxBD Field Descriptions TO1 TO2 DEF CSLXcntrlhbc = DataFreescale Semiconductor, Inc DC Electrical Characteristics AC Electrical CharacteristicsMII Receive Signal Timing RXD30, RXDV, RXER, Rxclk Electrical SpeciÞcationsMII Transmit Signal Timing TXD30, TXEN, TXER, Txclk MII Receive Signal TimingMII Transmit Signal Timing Num Characteristic Min Max UnitMII Async Inputs Signal Timing CRS, COL MII Async Inputs Signal TimingTxen Txer CRS, COLShows the MII serial management channel timing diagram MII Serial Management Channel TimingFollowing pins are marked as spare on MPC860T Pin AssignmentsFreescale Semiconductor, Inc Freescale Semiconductor, Inc For More Information On This Product
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