Freescale Semiconductor MPC860T REJECT3, MIITXD2, REJECT4, MIITXD1, Miitxen, Miicrs, Miicol

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Freescale Semiconductor, Inc...

 

 

 

 

Freescale Semiconductor, Inc.

 

 

 

 

Table 2-1. FEC Signal Descriptions (Continued)

 

 

 

 

 

 

Name

Pin

Description

 

Number

 

 

 

 

 

 

 

 

 

PD[4]

U16

General-purpose I/O port D bit 4ÑThis is bit 4 of the general-purpose I/O port D.

 

 

 

 

 

 

REJECT3

 

 

 

 

 

Reject 3ÑThis input to SCC3 allows a CAM to reject the current Ethernet frame after it

 

MII_TXD[2]

 

 

 

determines the frame address did not match.

 

 

 

 

 

 

 

 

 

 

 

 

 

MII transmit data 2ÑOutput signal TXD[2] represents bit 2 of the nibble of data when TX_EN

 

 

 

 

is asserted and has no meaning when TX_EN is negated.

 

 

 

 

 

PD[3]

W16

General-purpose I/O port D bit 3ÑThis is bit 3 of the general-purpose I/O port D.

 

REJECT4

 

 

 

 

 

 

Reject 4ÑThis input to SCC4 allows a CAM to reject the current Ethernet frame after it

 

MII_TXD[1]

 

 

 

determines the frame address did not match.

 

 

 

 

 

 

 

 

 

 

 

 

 

MII transmit data 1ÑOutput signal TXD[1] represents bit 1 of the nibble of data when TX_EN

 

 

 

 

is asserted and has no meaning when TX_EN is negated.

 

 

 

 

 

MII_TX_EN

V15

MII transmit enableÑOutput signal TX_EN indicates when there are valid nibbles being

 

 

 

 

presented on the MII. This signal is asserted with the Þrst nibble of preamble and is negated

 

 

 

 

prior to the Þrst TX_CLK following the Þnal nibble of the frame.

 

 

 

 

Note the following:

 

 

 

 

For 860T rev D.1, a 10-kΩpull-down resistor must be used with MII_TX_EN, which is

 

 

 

 

three-stated following reset until ECNTRL[FEC_PINMUX] is set.

 

 

 

 

For 860T rev D.2 and later, MII_TX_EN is a dedicated output and no pull-down resister is

 

 

 

 

required.

 

 

 

 

For 860T rev E.x (planned), MII_TX_EN resets to three-state with a weak internal

 

 

 

 

pull-down to ensure compatibility with 860 applications that may have tied SPARE3 (V15)

 

 

 

 

to VCC or GND. This pin will be 3-V only and must not be pulled up to +5 V.

 

 

 

 

 

MII_CRS

B7

MII carrier receive senseÑWhen input signal CRS is asserted the transmit or receive

 

 

 

 

medium is not idle. In the event of a collision, CRS will remain asserted through the duration

 

 

 

 

of the collision.

 

 

 

 

 

MII_COL

H4

MII collisionÑInput signal COL is asserted upon detection of a collision, and will remain

 

 

 

 

asserted while the collision persists. The behavior of this signal is not speciÞed for full-duplex

 

 

 

 

mode.

 

 

 

 

 

MII_MDIO

H18

MII management dataÑBidirectional signal, MDIO transfers control information between the

 

 

 

 

PHY and MAC. Transitions synchronously to MDC.

 

 

 

 

 

MOTOROLAChapter 2. FEC External Signals2-3

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Contents Freescale Semiconductor, Inc MPC860T Rev. D Fast Ethernet ControllerMotorola Literature Distribution Centers Contents Parallel I/O Ports Contents Paragraph Title Number Title Number IllustrationsViii MPC860T Rev. D Fast Ethernet Controller Supplement Tables Number Document Revision History Document Revision HistoryOverview Lists signiÞcant changes between revisions of this documentComparison with the MPC860 Features1 MPC860TBlock Diagram System Interface Unit SIU Embedded PowerPC Processor CoreFast Ethernet Controller SIU Interrupt ConÞguration Glueless System DesignInc FEC Signal Descriptions Signal DescriptionsName Pin Description Miitxer L1RSYNCBMiimdc RXD3MIITXD1 REJECT3MIITXD2 REJECT4Freescale Semiconductor, Inc This chapter discusses the operation of the FEC MII SignalsSignal Description FEC Signal Name Transceiver ConnectionRXD0 Serial Mode Connections to the External TransceiverFEC Frame Transmission TXD0FEC Frame Reception CAM Interface FEC Command SetEthernet Address Recognition Rcntrlprom = Hash Table AlgorithmCollision Handling Inter-Packet Gap TimeInternal and External Loopback Ethernet Error-Handling ProcedureTransmission Errors Reception ErrorsReception Errors Port D Pin Functions Chapter Parallel I/O PortsShows the port D pin assignments Enabling MII ModeSignal Function Port D RegistersCLK Sdma RegistersBits Describes Sdcr ÞeldsSdcr Field Descriptions FRZ Faid RAIDAddress Name Description Section Parameter RAMBrießy describes each enter in the FEC parameter RAM FEC Parameter RAM Memory MapRAM Perfect Match Address Low Register Addrlow Describes the Addrhigh Þelds RAM Perfect Match Address High AddrhighRAM Hash Table High Hashtablehigh Describes the Addrlow ÞeldsHashhigh RAM Hash Table Low HashtablelowDescribes Hashtablehigh Þelds Hashtablehigh Field DescriptionsDescribes Rdesstart Þelds Beginning of RxBD Ring RdesstartBeginning of TxBD Ring Xdesstart Describes Hashtablelow ÞeldsDescribes Xdesstart Þelds Receive Buffer Size Register RbuffsizeXdesstart Field Descriptions Rbuffsize Field Descriptions Spare Fecpin Etheren Reset MUXEthernet Control Register Ecntrl Describes Rbuffsize ÞeldsFecpinmux Interrupt Event IEVENT/Interrupt Mask Register ImaskDescribes Ecntrl Þelds Ecntrl Field DescriptionsHberr Ethernet Interrupt Vector Register IvecRfint to notify at the end of frame 10. IEVENT/IMASK Field DescriptionsIlevel RxBD Active Register Rdesactive11 describes Ivec Þelds 11. Ivec Field Descriptions12 describes Rdesactive Þelds TxBD Active Register Xdesactive12. Rdesactive Field Descriptions 13 describes Xdesactive Þelds MII Management Frame Register Miidata13. Xdesactive Field Descriptions 14. Miidata Field Descriptions 14 describes Miidata ÞeldsDispreamble Miispeed MII Speed Control Register Miispeed15 describes Miispeed Þelds 15. Miispeed Field Descriptions17. Rbound Field Descriptions Fifo Receive Bound Register Rbound17 describes Rbound Þelds 16. Programming Examples for Miispeed Register18. Rfstart Field Descriptions Fifo Receive Start Register RfstartTransmit Watermark Register Xwmrk 18 describes Rñfstart Þelds19 bit Þeld descriptions for Xwmrk Fifo Transmit Start Register Xfstart19. Xwmrk Field Descriptions DATABO0 DATABO1 DESCBO0 DESCBO1 FC1 FC2 FC3 DMA Function Code Register Funcode20 describes Xfstart Þelds 20. Xfstart Field DescriptionsDescbo Receive Control Register Rcntrl21 describes Funcode Þelds 21. Funcode Field DescriptionsBcrej Receive Hash Register Rhash22 describes Rcntrl Þelds 22. Rcntrl Field Descriptions23. Rhash Field Descriptions Transmit Control Register Xcntrl22 describes Rhash Þelds 24 describes Xcntrl Þelds25. Hardware Initialization User Initialization before Setting EcntrletherenInitialization Sequence Hardware InitializationStep Description 27. User Initialization before Setting EcntrletherenDescriptor Controller Initialization User Initialization after Asserting EcntrletherenStep 27. User Initialization after Setting EcntrletherenBuffer Descriptors BDs Ethernet Receive Buffer Descriptor RxBDRO1 RxBD format is shown in Table27. Receive Buffer Descriptor RxBD Field Description RO1 RO2 Data LengthTO1 TO2 DEF CSL Ethernet Transmit Buffer Descriptor TxBD29 describes TxBD Þelds 29. Transmit Buffer Descriptor TxBD Field DescriptionsData Xcntrlhbc =Freescale Semiconductor, Inc Electrical SpeciÞcations DC Electrical CharacteristicsAC Electrical Characteristics MII Receive Signal Timing RXD30, RXDV, RXER, RxclkNum Characteristic Min Max Unit MII Transmit Signal Timing TXD30, TXEN, TXER, TxclkMII Receive Signal Timing MII Transmit Signal TimingCRS, COL MII Async Inputs Signal Timing CRS, COLMII Async Inputs Signal Timing Txen TxerMII Serial Management Channel Timing Shows the MII serial management channel timing diagramMPC860T Pin Assignments Following pins are marked as spare onFreescale Semiconductor, Inc Freescale Semiconductor, Inc For More Information On This Product
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