Freescale Semiconductor MPC860T user manual RAM Perfect Match Address Low Register Addrlow

Page 34

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

Table 6-1. FEC Parameter RAM Memory Map (Continued)

Address

Name

Description

Section

 

 

 

 

0xE40

ECNTRL

Ethernet control register

6.2.8

 

 

 

 

0xE44

IEVENT

Interrupt event register

6.2.9

 

 

 

 

0xE48

IMASK

Interrupt mask register

6.2.9

 

 

 

 

0xE4C

IVEC

Interrupt level and vector status

6.2.10

 

 

 

 

0xE50

R_DES_ACTIVE

Receive ring updated ßag

6.2.11

 

 

 

 

0xE54

X_DES_ACTIVE

Transmit ring updated ßag

6.2.12

 

 

 

 

0xE80

MII_DATA

MII data register

6.2.13

 

 

 

 

0xE84

MII_SPEED

MII speed register

6.2.14

 

 

 

 

0xECC

R_BOUND

End of FIFO RAM (read-only)

6.2.15

 

 

 

 

0xED0

R_FSTART

Receive FIFO start address

6.2.16

 

 

 

 

0xEE4

X_WMRK

Transmit Watermark

6.2.17

 

 

 

 

0xEEC

X_FSTART

Transmit FIFO start address

6.2.18

 

 

 

 

0xF34

FUN_CODE

Function code to SDMA

6.2.19

 

 

 

 

0xF44

R_CNTRL

Receive control register

6.2.20

 

 

 

 

0xF48

R_HASH

Receive hash register

6.2.21

 

 

 

 

0xF84

X_CNTRL

Transmit control register

6.2.22

 

 

 

 

6.2.1 RAM Perfect Match Address Low Register (ADDR_LOW)

The ADDR_LOW register, shown in Figure 6-1, is written by and must be initialized by the user. It contains the lower 32 bits of the 48-bit address used in the address recognition process to compare with the destination address Þeld of the receive frames.

Bits

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Field

 

 

ADDR_LOW BYTE 0

 

 

 

 

ADDR_LOW BYTE 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

UndeÞned

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R/W

 

 

 

 

 

 

 

Read/write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Addr

 

 

 

 

 

 

 

0xE00

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bits

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Field

 

 

ADDR_LOW BYTE 2

 

 

 

 

ADDR_LOW BYTE 3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

UndeÞned

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R/W

 

 

 

 

 

 

 

Read/write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Addr

 

 

 

 

 

 

 

0xE02

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 6-1. ADDR_LOW Register

6-2MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA

PRELIMINARYÑSUBJECTFor ore nformationTO CHANGEOn ThisWITHOUTProduct,NOTICE

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Contents MPC860T Rev. D Fast Ethernet Controller Freescale Semiconductor, IncMotorola Literature Distribution Centers Contents Parallel I/O Ports Contents Paragraph Title Number Illustrations Title NumberViii MPC860T Rev. D Fast Ethernet Controller Supplement Tables Number Lists signiÞcant changes between revisions of this document Document Revision HistoryOverview Document Revision HistoryFeatures Comparison with the MPC8601 MPC860TBlock Diagram System Interface Unit SIU Embedded PowerPC Processor CoreFast Ethernet Controller Glueless System Design SIU Interrupt ConÞgurationInc FEC Signal Descriptions Signal DescriptionsName Pin Description RXD3 L1RSYNCBMiimdc MiitxerREJECT4 REJECT3MIITXD2 MIITXD1Freescale Semiconductor, Inc Transceiver Connection MII SignalsSignal Description FEC Signal Name This chapter discusses the operation of the FECTXD0 Serial Mode Connections to the External TransceiverFEC Frame Transmission RXD0FEC Frame Reception CAM Interface FEC Command SetEthernet Address Recognition Hash Table Algorithm Rcntrlprom =Inter-Packet Gap Time Collision HandlingReception Errors Ethernet Error-Handling ProcedureTransmission Errors Internal and External LoopbackReception Errors Chapter Parallel I/O Ports Port D Pin FunctionsPort D Registers Enabling MII ModeSignal Function Shows the port D pin assignmentsSdma Registers CLKFRZ Faid RAID Describes Sdcr ÞeldsSdcr Field Descriptions BitsFEC Parameter RAM Memory Map Parameter RAMBrießy describes each enter in the FEC parameter RAM Address Name Description SectionRAM Perfect Match Address Low Register Addrlow Describes the Addrlow Þelds RAM Perfect Match Address High AddrhighRAM Hash Table High Hashtablehigh Describes the Addrhigh ÞeldsHashtablehigh Field Descriptions RAM Hash Table Low HashtablelowDescribes Hashtablehigh Þelds HashhighDescribes Hashtablelow Þelds Beginning of RxBD Ring RdesstartBeginning of TxBD Ring Xdesstart Describes Rdesstart ÞeldsDescribes Xdesstart Þelds Receive Buffer Size Register RbuffsizeXdesstart Field Descriptions Describes Rbuffsize Þelds Spare Fecpin Etheren Reset MUXEthernet Control Register Ecntrl Rbuffsize Field DescriptionsEcntrl Field Descriptions Interrupt Event IEVENT/Interrupt Mask Register ImaskDescribes Ecntrl Þelds Fecpinmux10. IEVENT/IMASK Field Descriptions Ethernet Interrupt Vector Register IvecRfint to notify at the end of frame Hberr11. Ivec Field Descriptions RxBD Active Register Rdesactive11 describes Ivec Þelds Ilevel12 describes Rdesactive Þelds TxBD Active Register Xdesactive12. Rdesactive Field Descriptions 13 describes Xdesactive Þelds MII Management Frame Register Miidata13. Xdesactive Field Descriptions 14 describes Miidata Þelds 14. Miidata Field Descriptions15. Miispeed Field Descriptions MII Speed Control Register Miispeed15 describes Miispeed Þelds Dispreamble Miispeed16. Programming Examples for Miispeed Register Fifo Receive Bound Register Rbound17 describes Rbound Þelds 17. Rbound Field Descriptions18 describes Rñfstart Þelds Fifo Receive Start Register RfstartTransmit Watermark Register Xwmrk 18. Rfstart Field Descriptions19 bit Þeld descriptions for Xwmrk Fifo Transmit Start Register Xfstart19. Xwmrk Field Descriptions 20. Xfstart Field Descriptions DMA Function Code Register Funcode20 describes Xfstart Þelds DATABO0 DATABO1 DESCBO0 DESCBO1 FC1 FC2 FC321. Funcode Field Descriptions Receive Control Register Rcntrl21 describes Funcode Þelds Descbo22. Rcntrl Field Descriptions Receive Hash Register Rhash22 describes Rcntrl Þelds Bcrej24 describes Xcntrl Þelds Transmit Control Register Xcntrl22 describes Rhash Þelds 23. Rhash Field DescriptionsHardware Initialization User Initialization before Setting EcntrletherenInitialization Sequence 25. Hardware InitializationUser Initialization after Asserting Ecntrletheren 27. User Initialization before Setting EcntrletherenDescriptor Controller Initialization Step DescriptionEthernet Receive Buffer Descriptor RxBD 27. User Initialization after Setting EcntrletherenBuffer Descriptors BDs StepRO1 RO2 Data Length RxBD format is shown in Table27. Receive Buffer Descriptor RxBD Field Description RO129. Transmit Buffer Descriptor TxBD Field Descriptions Ethernet Transmit Buffer Descriptor TxBD29 describes TxBD Þelds TO1 TO2 DEF CSLXcntrlhbc = DataFreescale Semiconductor, Inc MII Receive Signal Timing RXD30, RXDV, RXER, Rxclk DC Electrical CharacteristicsAC Electrical Characteristics Electrical SpeciÞcationsMII Transmit Signal Timing MII Transmit Signal Timing TXD30, TXEN, TXER, TxclkMII Receive Signal Timing Num Characteristic Min Max UnitTxen Txer MII Async Inputs Signal Timing CRS, COLMII Async Inputs Signal Timing CRS, COLShows the MII serial management channel timing diagram MII Serial Management Channel TimingFollowing pins are marked as spare on MPC860T Pin AssignmentsFreescale Semiconductor, Inc Freescale Semiconductor, Inc For More Information On This Product
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