Freescale Semiconductor MPC860T user manual FEC Parameter RAM Memory Map

Page 33

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

Chapter 6

Programming Model

This chapter gives an overview of the MPC860T implementation of the Fast Ethernet controller (FEC) registers, buffer descriptors (BDs), and initialization.

6.1 Overview

The FEC software model is similar to that used by the 10-Mbps Ethernet implemented on the MPC860 core device. To support higher data rates, the FEC has a different internal architecture, which changes the programming model slightly. However, efforts have been taken to minimize the differences required by the interrupt handlers. The FECÕs registers are very different from those of the CPM-based internal Ethernet controller.

The FEC is programmed by a combination of control/status registers (CSRs) and BDs. The CSRs are used for mode control and to extract global status information. The BDs are used to pass data buffers and related buffer information between hardware and software.

Some registers are located in on-chip RAM. All on-chip registers, whether located in RAM or in hardware, must be accessed using big-endian mode, therefore, descriptions in this chapter assume big-endian byte ordering. There is no support for little-endian in the FEC.

6.2 Parameter RAM

Table 6-1 brießy describes each enter in the FEC parameter RAM.

Table 6-1. FEC Parameter RAM Memory Map

 

Address

Name

Description

Section

 

 

 

 

 

 

 

 

0xE00

ADDR_LOW

Lower 32 bits of address

6.2.1

 

 

 

 

 

 

 

 

0xE04

ADDR_HIGH

Upper 16 bits of address

6.2.2

 

 

 

 

 

 

 

 

0xE08

HASH_TABLE_HIGH

Upper 32 bits of hash table

6.2.3

 

 

 

 

 

 

 

 

0xE0C

HASH_TABLE_LOW

Lower 32 bits of hash table

6.2.4

 

 

 

 

 

 

 

 

0xE10

R_DES_START

Pointer to beginning of RxBD ring

6.2.5

 

 

 

 

 

 

 

 

0xE14

X_DES_START

Pointer to beginning of TxBD ring

6.2.6

 

 

 

 

 

 

 

 

0xE18

R_BUFF_SIZE

Receive buffer size

6.2.7

 

 

 

 

 

 

 

 

 

 

 

 

 

MOTOROLAChapter 6.Programming Model6-1

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Contents
Freescale Semiconductor, Inc MPC860T Rev. D Fast Ethernet ControllerMotorola Literature Distribution Centers Contents Parallel I/O Ports Contents Paragraph Title Number Title Number IllustrationsViii MPC860T Rev. D Fast Ethernet Controller Supplement Tables Number Overview Document Revision HistoryLists signiÞcant changes between revisions of this document Document Revision HistoryComparison with the MPC860 Features1 MPC860TBlock Diagram Embedded PowerPC Processor Core System Interface Unit SIUFast Ethernet Controller SIU Interrupt ConÞguration Glueless System DesignInc Signal Descriptions FEC Signal DescriptionsName Pin Description Miimdc L1RSYNCBRXD3 MiitxerMIITXD2 REJECT3REJECT4 MIITXD1Freescale Semiconductor, Inc Signal Description FEC Signal Name MII SignalsTransceiver Connection This chapter discusses the operation of the FECFEC Frame Transmission Serial Mode Connections to the External TransceiverTXD0 RXD0FEC Frame Reception FEC Command Set CAM InterfaceEthernet Address Recognition Rcntrlprom = Hash Table AlgorithmCollision Handling Inter-Packet Gap TimeTransmission Errors Ethernet Error-Handling ProcedureReception Errors Internal and External LoopbackReception Errors Port D Pin Functions Chapter Parallel I/O PortsSignal Function Enabling MII ModePort D Registers Shows the port D pin assignmentsCLK Sdma RegistersSdcr Field Descriptions Describes Sdcr ÞeldsFRZ Faid RAID BitsBrießy describes each enter in the FEC parameter RAM Parameter RAMFEC Parameter RAM Memory Map Address Name Description SectionRAM Perfect Match Address Low Register Addrlow RAM Hash Table High Hashtablehigh RAM Perfect Match Address High AddrhighDescribes the Addrlow Þelds Describes the Addrhigh ÞeldsDescribes Hashtablehigh Þelds RAM Hash Table Low HashtablelowHashtablehigh Field Descriptions HashhighBeginning of TxBD Ring Xdesstart Beginning of RxBD Ring RdesstartDescribes Hashtablelow Þelds Describes Rdesstart ÞeldsReceive Buffer Size Register Rbuffsize Describes Xdesstart ÞeldsXdesstart Field Descriptions Ethernet Control Register Ecntrl Spare Fecpin Etheren Reset MUXDescribes Rbuffsize Þelds Rbuffsize Field DescriptionsDescribes Ecntrl Þelds Interrupt Event IEVENT/Interrupt Mask Register ImaskEcntrl Field Descriptions FecpinmuxRfint to notify at the end of frame Ethernet Interrupt Vector Register Ivec10. IEVENT/IMASK Field Descriptions Hberr11 describes Ivec Þelds RxBD Active Register Rdesactive11. Ivec Field Descriptions IlevelTxBD Active Register Xdesactive 12 describes Rdesactive Þelds12. Rdesactive Field Descriptions MII Management Frame Register Miidata 13 describes Xdesactive Þelds13. Xdesactive Field Descriptions 14. Miidata Field Descriptions 14 describes Miidata Þelds15 describes Miispeed Þelds MII Speed Control Register Miispeed15. Miispeed Field Descriptions Dispreamble Miispeed17 describes Rbound Þelds Fifo Receive Bound Register Rbound16. Programming Examples for Miispeed Register 17. Rbound Field DescriptionsTransmit Watermark Register Xwmrk Fifo Receive Start Register Rfstart18 describes Rñfstart Þelds 18. Rfstart Field DescriptionsFifo Transmit Start Register Xfstart 19 bit Þeld descriptions for Xwmrk19. Xwmrk Field Descriptions 20 describes Xfstart Þelds DMA Function Code Register Funcode20. Xfstart Field Descriptions DATABO0 DATABO1 DESCBO0 DESCBO1 FC1 FC2 FC321 describes Funcode Þelds Receive Control Register Rcntrl21. Funcode Field Descriptions Descbo22 describes Rcntrl Þelds Receive Hash Register Rhash22. Rcntrl Field Descriptions Bcrej22 describes Rhash Þelds Transmit Control Register Xcntrl24 describes Xcntrl Þelds 23. Rhash Field DescriptionsInitialization Sequence User Initialization before Setting EcntrletherenHardware Initialization 25. Hardware InitializationDescriptor Controller Initialization 27. User Initialization before Setting EcntrletherenUser Initialization after Asserting Ecntrletheren Step DescriptionBuffer Descriptors BDs 27. User Initialization after Setting EcntrletherenEthernet Receive Buffer Descriptor RxBD Step27. Receive Buffer Descriptor RxBD Field Description RxBD format is shown in TableRO1 RO2 Data Length RO129 describes TxBD Þelds Ethernet Transmit Buffer Descriptor TxBD29. Transmit Buffer Descriptor TxBD Field Descriptions TO1 TO2 DEF CSLData Xcntrlhbc =Freescale Semiconductor, Inc AC Electrical Characteristics DC Electrical CharacteristicsMII Receive Signal Timing RXD30, RXDV, RXER, Rxclk Electrical SpeciÞcationsMII Receive Signal Timing MII Transmit Signal Timing TXD30, TXEN, TXER, TxclkMII Transmit Signal Timing Num Characteristic Min Max UnitMII Async Inputs Signal Timing MII Async Inputs Signal Timing CRS, COLTxen Txer CRS, COLMII Serial Management Channel Timing Shows the MII serial management channel timing diagramMPC860T Pin Assignments Following pins are marked as spare onFreescale Semiconductor, Inc Freescale Semiconductor, Inc For More Information On This Product
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