Freescale Semiconductor MPC860T user manual RAM Perfect Match Address High Addrhigh

Page 35

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

Table 6-2 describes the ADDR_LOW Þelds.

 

 

Table 6-2. ADDR_LOW Field Descriptions

 

 

 

Bits

Name

Description

 

 

 

0Ð31

ADDR_LOW

Bytes in the 6-byte address: 0 (bits 0Ð7), 1 (bits 8Ð15), 2 (bits 16Ð23) and 3 (bits 24Ð31)

 

 

 

6.2.2 RAM Perfect Match Address High (ADDR_HIGH)

The ADDR_HIGH register, shown in Figure 6-2, is written by and must be initialized by the user. It contains bytes 4 and 5 of the 6-byte address used to compare with the destination address Þeld of the receive frames. Byte 0 is the Þrst byte sent at the start of the frame.

Bits

0

1

2

3

4

5

6

7

 

8

9

10

11

12

13

14

15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Field

 

 

ADDR_HIGH BYTE 4

 

 

 

 

 

ADDR_HIGH BYTE 5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

UndeÞned

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R/W

 

 

 

 

 

 

 

Read/write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Addr

 

 

 

 

 

 

 

0xE04

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bits

16

17

18

19

20

21

22

23

 

24

25

26

27

28

29

30

31

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Field

 

 

 

 

 

 

 

 

Ñ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

UndeÞned

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R/W

 

 

 

 

 

 

 

Read/write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Addr

 

 

 

 

 

 

 

0xE06

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 6-2. ADDR_HIGH Register

Table 6-3 describes the ADDR_HIGH Þelds.

Table 6-3. ADDR_HIGH Field Descriptions

Bits

Name

Description

 

 

 

0Ð15

ADDR_HIGH

Bytes of the 6-byte address: 4 (bits 0Ð7) and 5 (bits 8Ð15)

 

 

 

16Ð31

Ñ

Reserved. Should be cleared by the host processor.

 

 

 

6.2.3 RAM Hash Table High (HASH_TABLE_HIGH)

The HASH_TABLE_HIGH register, shown in Figure 6-3, contains the upper 32 bits of the 64-bit hash table used in address recognition for receive frames with a multicast address. It is written by and must be initialized by the user

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Contents Freescale Semiconductor, Inc MPC860T Rev. D Fast Ethernet ControllerMotorola Literature Distribution Centers Contents Parallel I/O Ports Contents Paragraph Title Number Title Number IllustrationsViii MPC860T Rev. D Fast Ethernet Controller Supplement Tables Number Document Revision History Document Revision HistoryOverview Lists signiÞcant changes between revisions of this documentComparison with the MPC860 Features1 MPC860TBlock Diagram Fast Ethernet Controller Embedded PowerPC Processor CoreSystem Interface Unit SIU SIU Interrupt ConÞguration Glueless System DesignInc Name Pin Description Signal DescriptionsFEC Signal Descriptions Miitxer L1RSYNCBMiimdc RXD3MIITXD1 REJECT3MIITXD2 REJECT4Freescale Semiconductor, Inc This chapter discusses the operation of the FEC MII SignalsSignal Description FEC Signal Name Transceiver ConnectionRXD0 Serial Mode Connections to the External TransceiverFEC Frame Transmission TXD0FEC Frame Reception Ethernet Address Recognition FEC Command SetCAM Interface Rcntrlprom = Hash Table AlgorithmCollision Handling Inter-Packet Gap TimeInternal and External Loopback Ethernet Error-Handling ProcedureTransmission Errors Reception ErrorsReception Errors Port D Pin Functions Chapter Parallel I/O PortsShows the port D pin assignments Enabling MII ModeSignal Function Port D RegistersCLK Sdma RegistersBits Describes Sdcr ÞeldsSdcr Field Descriptions FRZ Faid RAIDAddress Name Description Section Parameter RAMBrießy describes each enter in the FEC parameter RAM FEC Parameter RAM Memory MapRAM Perfect Match Address Low Register Addrlow Describes the Addrhigh Þelds RAM Perfect Match Address High AddrhighRAM Hash Table High Hashtablehigh Describes the Addrlow ÞeldsHashhigh RAM Hash Table Low HashtablelowDescribes Hashtablehigh Þelds Hashtablehigh Field DescriptionsDescribes Rdesstart Þelds Beginning of RxBD Ring RdesstartBeginning of TxBD Ring Xdesstart Describes Hashtablelow ÞeldsXdesstart Field Descriptions Receive Buffer Size Register RbuffsizeDescribes Xdesstart Þelds Rbuffsize Field Descriptions Spare Fecpin Etheren Reset MUXEthernet Control Register Ecntrl Describes Rbuffsize ÞeldsFecpinmux Interrupt Event IEVENT/Interrupt Mask Register ImaskDescribes Ecntrl Þelds Ecntrl Field DescriptionsHberr Ethernet Interrupt Vector Register IvecRfint to notify at the end of frame 10. IEVENT/IMASK Field DescriptionsIlevel RxBD Active Register Rdesactive11 describes Ivec Þelds 11. Ivec Field Descriptions12. Rdesactive Field Descriptions TxBD Active Register Xdesactive12 describes Rdesactive Þelds 13. Xdesactive Field Descriptions MII Management Frame Register Miidata13 describes Xdesactive Þelds 14. Miidata Field Descriptions 14 describes Miidata ÞeldsDispreamble Miispeed MII Speed Control Register Miispeed15 describes Miispeed Þelds 15. Miispeed Field Descriptions17. Rbound Field Descriptions Fifo Receive Bound Register Rbound17 describes Rbound Þelds 16. Programming Examples for Miispeed Register18. Rfstart Field Descriptions Fifo Receive Start Register RfstartTransmit Watermark Register Xwmrk 18 describes Rñfstart Þelds19. Xwmrk Field Descriptions Fifo Transmit Start Register Xfstart19 bit Þeld descriptions for Xwmrk DATABO0 DATABO1 DESCBO0 DESCBO1 FC1 FC2 FC3 DMA Function Code Register Funcode20 describes Xfstart Þelds 20. Xfstart Field DescriptionsDescbo Receive Control Register Rcntrl21 describes Funcode Þelds 21. Funcode Field DescriptionsBcrej Receive Hash Register Rhash22 describes Rcntrl Þelds 22. Rcntrl Field Descriptions23. Rhash Field Descriptions Transmit Control Register Xcntrl22 describes Rhash Þelds 24 describes Xcntrl Þelds25. Hardware Initialization User Initialization before Setting EcntrletherenInitialization Sequence Hardware InitializationStep Description 27. User Initialization before Setting EcntrletherenDescriptor Controller Initialization User Initialization after Asserting EcntrletherenStep 27. User Initialization after Setting EcntrletherenBuffer Descriptors BDs Ethernet Receive Buffer Descriptor RxBDRO1 RxBD format is shown in Table27. Receive Buffer Descriptor RxBD Field Description RO1 RO2 Data LengthTO1 TO2 DEF CSL Ethernet Transmit Buffer Descriptor TxBD29 describes TxBD Þelds 29. Transmit Buffer Descriptor TxBD Field DescriptionsData Xcntrlhbc =Freescale Semiconductor, Inc Electrical SpeciÞcations DC Electrical CharacteristicsAC Electrical Characteristics MII Receive Signal Timing RXD30, RXDV, RXER, RxclkNum Characteristic Min Max Unit MII Transmit Signal Timing TXD30, TXEN, TXER, TxclkMII Receive Signal Timing MII Transmit Signal TimingCRS, COL MII Async Inputs Signal Timing CRS, COLMII Async Inputs Signal Timing Txen TxerMII Serial Management Channel Timing Shows the MII serial management channel timing diagramMPC860T Pin Assignments Following pins are marked as spare onFreescale Semiconductor, Inc Freescale Semiconductor, Inc For More Information On This Product
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