Freescale Semiconductor MPC860T Ethernet Transmit Buffer Descriptor TxBD, describes TxBD Þelds

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Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

Table 6-27. Receive Buffer Descriptor (RxBD) Field Description (Continued)

Bits

Name

Description

 

 

 

14

OV

Overrun, written by FEC. A receive FIFO overrun occurred during frame reception. If OV = 1,

 

 

the other status bits, M, LG, NO, SH, CR, and CL lose their normal meaning and are cleared.

 

 

This bit is valid only if the L bit is set.

 

 

 

15

TR

Truncate. Set if the receive frame is truncated (≥ 2 Kbytes).

 

 

 

Offset+2

Data

Data length, written by FEC. Data length is the number of octets written by the FEC into this

 

length

BDÕs buffer if L = 0 (the value = R_BUFF_SIZE), or the length of the frame including CRC if

 

 

L = 1. It is written by the FEC once as the BD is closed.

 

 

 

Offset+4

Rx

Rx buffer pointer A[0Ð31], written by user. The receive buffer pointer, which always points to the

 

buffer

Þrst location of the associated buffer, must always be a multiple of 16. The buffer must reside in

 

pointer

memory external to the FEC.

 

 

 

6.4.2 Ethernet Transmit Buffer Descriptor (TxBD)

Data is presented to the FEC for transmission by arranging it in buffers referenced by the channelÕs TxBDs. The FEC conÞrms transmission or indicates error conditions using BDs to inform the host that the buffers have been serviced. The user initializes TxBD[R,W,L,TC], the length (in bytes), and the buffer pointer.

¥If L = 0, the FEC clears the R bit when the buffer is accessed. Status bits are not modiÞed.

¥If L = 1, the FEC clears the R bit and modiÞes the DEF, HB, LC, RL, RC, UN, and CSL status bits after the buffer is accessed and frame transmission completes.

The TxBD is shown in Figure 6-24.

Figure 6-24. Transmit Buffer Descriptor (TxBD)

 

0

1

2

3

4

5

6

7

8

 

9

10

11

12

13

14

15

+0

R

TO1

W

TO2

L

TC

DEF

 

HB

LC

 

RL

 

RC

 

 

UN

CSL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

+2

 

 

 

 

 

 

 

DATA LENGTH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

+4

 

 

 

 

 

Tx Data Buffer Pointer A[0Ð15]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

+6

 

 

 

 

 

Tx Data Buffer Pointer A[16Ð31]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 6-29 describes TxBD Þelds.

Table 6-29. Transmit Buffer Descriptor (TxBD) Field Descriptions

Bits

Name

 

Description

 

 

 

0

R

Ready, written by FEC and user.

 

 

0

The buffer associated with this BD is not ready for transmission. The user can manipulate this

 

 

 

BD or its associated buffer. The FEC clears R after the buffer is sent or an error occurs.

 

 

1

The user-prepared buffer has not been sent or is being sent. The user cannot update the BD

 

 

 

while R = 1.

 

 

 

1

TO1

Transmit software ownership bit. This Þeld is available for use by software. This read/write bit is

 

 

not modiÞed by hardware and its value does not affect hardware.

 

 

 

 

6-26MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA

PRELIMINARYÑSUBJECTFor ore nformationTO CHANGEOn ThisWITHOUTProduct,NOTICE

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Contents MPC860T Rev. D Fast Ethernet Controller Freescale Semiconductor, IncMotorola Literature Distribution Centers Contents Parallel I/O Ports Contents Paragraph Title Number Illustrations Title NumberViii MPC860T Rev. D Fast Ethernet Controller Supplement Tables Number Lists signiÞcant changes between revisions of this document Document Revision HistoryOverview Document Revision HistoryFeatures Comparison with the MPC8601 MPC860TBlock Diagram System Interface Unit SIU Embedded PowerPC Processor CoreFast Ethernet Controller Glueless System Design SIU Interrupt ConÞgurationInc FEC Signal Descriptions Signal DescriptionsName Pin Description RXD3 L1RSYNCBMiimdc MiitxerREJECT4 REJECT3MIITXD2 MIITXD1Freescale Semiconductor, Inc Transceiver Connection MII SignalsSignal Description FEC Signal Name This chapter discusses the operation of the FECTXD0 Serial Mode Connections to the External TransceiverFEC Frame Transmission RXD0FEC Frame Reception CAM Interface FEC Command SetEthernet Address Recognition Hash Table Algorithm Rcntrlprom =Inter-Packet Gap Time Collision HandlingReception Errors Ethernet Error-Handling ProcedureTransmission Errors Internal and External LoopbackReception Errors Chapter Parallel I/O Ports Port D Pin FunctionsPort D Registers Enabling MII ModeSignal Function Shows the port D pin assignmentsSdma Registers CLKFRZ Faid RAID Describes Sdcr ÞeldsSdcr Field Descriptions BitsFEC Parameter RAM Memory Map Parameter RAMBrießy describes each enter in the FEC parameter RAM Address Name Description SectionRAM Perfect Match Address Low Register Addrlow Describes the Addrlow Þelds RAM Perfect Match Address High AddrhighRAM Hash Table High Hashtablehigh Describes the Addrhigh ÞeldsHashtablehigh Field Descriptions RAM Hash Table Low HashtablelowDescribes Hashtablehigh Þelds HashhighDescribes Hashtablelow Þelds Beginning of RxBD Ring RdesstartBeginning of TxBD Ring Xdesstart Describes Rdesstart ÞeldsDescribes Xdesstart Þelds Receive Buffer Size Register RbuffsizeXdesstart Field Descriptions Describes Rbuffsize Þelds Spare Fecpin Etheren Reset MUXEthernet Control Register Ecntrl Rbuffsize Field DescriptionsEcntrl Field Descriptions Interrupt Event IEVENT/Interrupt Mask Register ImaskDescribes Ecntrl Þelds Fecpinmux10. IEVENT/IMASK Field Descriptions Ethernet Interrupt Vector Register IvecRfint to notify at the end of frame Hberr11. Ivec Field Descriptions RxBD Active Register Rdesactive11 describes Ivec Þelds Ilevel12 describes Rdesactive Þelds TxBD Active Register Xdesactive12. Rdesactive Field Descriptions 13 describes Xdesactive Þelds MII Management Frame Register Miidata13. Xdesactive Field Descriptions 14 describes Miidata Þelds 14. Miidata Field Descriptions15. Miispeed Field Descriptions MII Speed Control Register Miispeed15 describes Miispeed Þelds Dispreamble Miispeed16. Programming Examples for Miispeed Register Fifo Receive Bound Register Rbound17 describes Rbound Þelds 17. Rbound Field Descriptions18 describes Rñfstart Þelds Fifo Receive Start Register RfstartTransmit Watermark Register Xwmrk 18. Rfstart Field Descriptions19 bit Þeld descriptions for Xwmrk Fifo Transmit Start Register Xfstart19. Xwmrk Field Descriptions 20. Xfstart Field Descriptions DMA Function Code Register Funcode20 describes Xfstart Þelds DATABO0 DATABO1 DESCBO0 DESCBO1 FC1 FC2 FC321. Funcode Field Descriptions Receive Control Register Rcntrl21 describes Funcode Þelds Descbo22. Rcntrl Field Descriptions Receive Hash Register Rhash22 describes Rcntrl Þelds Bcrej24 describes Xcntrl Þelds Transmit Control Register Xcntrl22 describes Rhash Þelds 23. Rhash Field DescriptionsHardware Initialization User Initialization before Setting EcntrletherenInitialization Sequence 25. Hardware InitializationUser Initialization after Asserting Ecntrletheren 27. User Initialization before Setting EcntrletherenDescriptor Controller Initialization Step DescriptionEthernet Receive Buffer Descriptor RxBD 27. User Initialization after Setting EcntrletherenBuffer Descriptors BDs StepRO1 RO2 Data Length RxBD format is shown in Table27. Receive Buffer Descriptor RxBD Field Description RO129. Transmit Buffer Descriptor TxBD Field Descriptions Ethernet Transmit Buffer Descriptor TxBD29 describes TxBD Þelds TO1 TO2 DEF CSLXcntrlhbc = DataFreescale Semiconductor, Inc MII Receive Signal Timing RXD30, RXDV, RXER, Rxclk DC Electrical CharacteristicsAC Electrical Characteristics Electrical SpeciÞcationsMII Transmit Signal Timing MII Transmit Signal Timing TXD30, TXEN, TXER, TxclkMII Receive Signal Timing Num Characteristic Min Max UnitTxen Txer MII Async Inputs Signal Timing CRS, COLMII Async Inputs Signal Timing CRS, COLShows the MII serial management channel timing diagram MII Serial Management Channel TimingFollowing pins are marked as spare on MPC860T Pin AssignmentsFreescale Semiconductor, Inc Freescale Semiconductor, Inc For More Information On This Product
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