Freescale Semiconductor MPC860T Port D Registers, Enabling MII Mode, Port D Pin Assignment

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Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

Table 4-1 shows the port D pin assignments.

		Table 4-1. Port D Pin Assignment

			Signal Function
Signal
Signal	PDPAR = 0			PDPAR=1		Input to On-Chip
						Input to On-Chip
						Peripherals
			PDDIR=0		PDDIR=1	Peripherals
			PDDIR=0		PDDIR=1

PD15	PORT D15		L1TSYNCA		MII-RXD3 (I)	L1TSYNCA=GND

PD14	PORT D14		L1RSYNCA		MII-RXD2 (I)	L1RSYNCA=GND

PD13	PORT D13		L1TSYNCB		MII-RXD1 (I)	L1TSYNCB=GND

PD12	PORT D12		L1RSYNCB		MII-MDC (O)	L1RSYNCB=GND

PD11	PORT D11		RXD3		MII-TX-ERR (O)	RXD3 = GND

PD10	PORT D10		TXD3		MII-RXD0 (I)	Ñ

PD9	PORT D9		RXD4		MII-TXD0 (O)	RXD4 = GND

PD8	PORT D8		TXD4		MII-RX_CLK (I)	Ñ

PD7	PORT D7		MII-RX-RTS3\ERR(I)		Ñ

PD6	PORT D6		RTS4		MII-RXDV (I)	Ñ

PD5	PORT D5		REJECT2		MII-TXD3 (O)	REJECT2=VDD

PD4	PORT D4		REJECT3		MII-TXD2 (O)	REJECT3=VDD

PD3	PORT D3		REJECT4		MII-TXD1 (O)	REJECT4=VDD

4.1.1 Port D Registers

Port D has three memory-mapped, read/write, 16-bit control registers.

4.1.2 Enabling MII Mode

To enable MII mode, do the following:

1.Write 0x1FFF to PDPAR.

2.Write 0x1FFF to PDDIR.

4-2MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA

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Contents MPC860T Rev. D Fast Ethernet Controller Freescale Semiconductor, IncMotorola Literature Distribution Centers Contents Parallel I/O Ports Contents Paragraph Title Number Illustrations Title NumberViii MPC860T Rev. D Fast Ethernet Controller Supplement Tables Number Lists signiÞcant changes between revisions of this document Document Revision HistoryOverview Document Revision HistoryFeatures Comparison with the MPC8601 MPC860TBlock Diagram Embedded PowerPC Processor Core System Interface Unit SIUFast Ethernet Controller Glueless System Design SIU Interrupt ConÞgurationInc Signal Descriptions FEC Signal DescriptionsName Pin Description RXD3 L1RSYNCBMiimdc MiitxerREJECT4 REJECT3MIITXD2 MIITXD1Freescale Semiconductor, Inc Transceiver Connection MII SignalsSignal Description FEC Signal Name This chapter discusses the operation of the FECTXD0 Serial Mode Connections to the External TransceiverFEC Frame Transmission RXD0FEC Frame Reception FEC Command Set CAM InterfaceEthernet Address Recognition Hash Table Algorithm Rcntrlprom =Inter-Packet Gap Time Collision HandlingReception Errors Ethernet Error-Handling ProcedureTransmission Errors Internal and External LoopbackReception Errors Chapter Parallel I/O Ports Port D Pin FunctionsPort D Registers Enabling MII ModeSignal Function Shows the port D pin assignmentsSdma Registers CLKFRZ Faid RAID Describes Sdcr ÞeldsSdcr Field Descriptions BitsFEC Parameter RAM Memory Map Parameter RAMBrießy describes each enter in the FEC parameter RAM Address Name Description SectionRAM Perfect Match Address Low Register Addrlow Describes the Addrlow Þelds RAM Perfect Match Address High AddrhighRAM Hash Table High Hashtablehigh Describes the Addrhigh ÞeldsHashtablehigh Field Descriptions RAM Hash Table Low HashtablelowDescribes Hashtablehigh Þelds HashhighDescribes Hashtablelow Þelds Beginning of RxBD Ring RdesstartBeginning of TxBD Ring Xdesstart Describes Rdesstart ÞeldsReceive Buffer Size Register Rbuffsize Describes Xdesstart ÞeldsXdesstart Field Descriptions Describes Rbuffsize Þelds Spare Fecpin Etheren Reset MUXEthernet Control Register Ecntrl Rbuffsize Field DescriptionsEcntrl Field Descriptions Interrupt Event IEVENT/Interrupt Mask Register ImaskDescribes Ecntrl Þelds Fecpinmux10. IEVENT/IMASK Field Descriptions Ethernet Interrupt Vector Register IvecRfint to notify at the end of frame Hberr11. Ivec Field Descriptions RxBD Active Register Rdesactive11 describes Ivec Þelds IlevelTxBD Active Register Xdesactive 12 describes Rdesactive Þelds12. Rdesactive Field Descriptions MII Management Frame Register Miidata 13 describes Xdesactive Þelds13. Xdesactive Field Descriptions 14 describes Miidata Þelds 14. Miidata Field Descriptions15. Miispeed Field Descriptions MII Speed Control Register Miispeed15 describes Miispeed Þelds Dispreamble Miispeed16. Programming Examples for Miispeed Register Fifo Receive Bound Register Rbound17 describes Rbound Þelds 17. Rbound Field Descriptions18 describes Rñfstart Þelds Fifo Receive Start Register RfstartTransmit Watermark Register Xwmrk 18. Rfstart Field DescriptionsFifo Transmit Start Register Xfstart 19 bit Þeld descriptions for Xwmrk19. Xwmrk Field Descriptions 20. Xfstart Field Descriptions DMA Function Code Register Funcode20 describes Xfstart Þelds DATABO0 DATABO1 DESCBO0 DESCBO1 FC1 FC2 FC321. Funcode Field Descriptions Receive Control Register Rcntrl21 describes Funcode Þelds Descbo22. Rcntrl Field Descriptions Receive Hash Register Rhash22 describes Rcntrl Þelds Bcrej24 describes Xcntrl Þelds Transmit Control Register Xcntrl22 describes Rhash Þelds 23. Rhash Field DescriptionsHardware Initialization User Initialization before Setting EcntrletherenInitialization Sequence 25. Hardware InitializationUser Initialization after Asserting Ecntrletheren 27. User Initialization before Setting EcntrletherenDescriptor Controller Initialization Step DescriptionEthernet Receive Buffer Descriptor RxBD 27. User Initialization after Setting EcntrletherenBuffer Descriptors BDs StepRO1 RO2 Data Length RxBD format is shown in Table27. Receive Buffer Descriptor RxBD Field Description RO129. Transmit Buffer Descriptor TxBD Field Descriptions Ethernet Transmit Buffer Descriptor TxBD29 describes TxBD Þelds TO1 TO2 DEF CSLXcntrlhbc = DataFreescale Semiconductor, Inc MII Receive Signal Timing RXD30, RXDV, RXER, Rxclk DC Electrical CharacteristicsAC Electrical Characteristics Electrical SpeciÞcationsMII Transmit Signal Timing MII Transmit Signal Timing TXD30, TXEN, TXER, TxclkMII Receive Signal Timing Num Characteristic Min Max UnitTxen Txer MII Async Inputs Signal Timing CRS, COLMII Async Inputs Signal Timing CRS, COLShows the MII serial management channel timing diagram MII Serial Management Channel TimingFollowing pins are marked as spare on MPC860T Pin AssignmentsFreescale Semiconductor, Inc Freescale Semiconductor, Inc For More Information On This Product