Freescale Semiconductor MPC860T L1RSYNCB, Miimdc, RXD3, Miitxer, TXD3, MIIRXD0, RXD4, MIITXD0

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Freescale Semiconductor, Inc...

 

 

 

 

 

Freescale Semiconductor, Inc.

 

 

 

 

 

 

 

Table 2-1. FEC Signal Descriptions (Continued)

 

 

 

 

 

 

 

 

 

 

 

 

Name

Pin

Description

 

 

 

 

Number

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PD[12]

R16

General-purpose I/O port D bit 12ÑThis is bit 12 of the general-purpose I/O port D.

 

 

 

L1RSYNCB

 

 

 

 

 

 

 

L1RSYNCBÑInput receive data sync signal to the TDM channel B.

 

 

 

 

MII_MDC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MII management data clockÑOutput clock provides a timing reference to the PHY for data

 

 

 

 

 

 

transfers on the MDIO signal.

 

 

 

 

 

 

 

 

 

 

PD[11]

T16

General-purpose I/O port D bit 11ÑThis is bit 11 of the general-purpose I/O port D.

 

 

 

RXD3

 

 

 

 

 

 

 

RXD3ÑReceive data for serial channel 3.

 

 

 

 

MII_TX_ER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MII transmit errorÑOutput signal when asserted for one or more clock cycles while TX_EN is

 

 

 

 

 

 

asserted shall cause the PHY to transmit one or more illegal symbols. Asserting TX_ER has

 

 

 

 

 

 

no effect when operating at 10 Mbps or when TX_EN is negated.

 

 

 

 

 

 

 

 

 

 

PD[10]

W18

General-purpose I/O port D bit 10ÑThis is bit 10 of the general-purpose I/O port D.

 

 

 

TXD3

 

 

 

 

 

 

 

TXD3ÑTransmit data for serial channel 3.

 

 

 

 

MII_RXD[0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MII receive data 0ÑInput signal RXD[0] represents bit 0 of the nibble of data to be

 

 

 

 

 

 

transferred from the PHY to the MAC when RX_DV is asserted. In 10 Mbps serial mode,

 

 

 

 

 

 

RXD[0] is used and RXD[1Ð3] are ignored.

 

 

 

 

 

 

 

 

 

 

PD[9]

V17

General-purpose I/O port D bit 9ÑThis is bit 9 of the general-purpose I/O port D.

 

 

 

RXD4

 

 

 

 

 

 

 

RXD4ÑReceive data for serial channel 4.

 

 

 

 

MII_TXD[0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MII transmit data 0ÑOutput signal TXD[0] represents bit 0 of the nibble of data when TX_EN

 

 

 

 

 

 

is asserted and has no meaning when TX_EN is negated. In 10Mbps serial mode, TXD[0] is

 

 

 

 

 

 

used and TXD[1Ð3] are ignored.

 

 

 

 

 

 

 

 

 

 

PD[8]

W17

General-purpose I/O port D bit 8ÑThis is bit 8 of the general-purpose I/O port D.

 

 

 

TXD4

 

 

 

 

 

 

 

TXD4ÑTransmit data for serial channel 4.

 

 

 

 

MII_RX_CLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MII receive clockÑInput clock which provides a timing reference for RX_DV, RXD, and

 

 

 

 

 

 

RX_ER.

 

 

 

 

 

 

 

 

 

 

PD[7]

T15

General-purpose I/O port D bit 7ÑThis is bit 7 of the general-purpose I/O port D.

 

 

 

RTS3

 

 

 

 

 

 

 

RTS3ÑActive-low request to send output indicates that SCC3 is ready to transmit data.

 

 

 

MII_RX_ER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MII receive errorÑWhen Input signal RX_ER and RX_DV are asserted, the PHY has

 

 

 

 

 

 

detected an error in the current frame. When RX_DV is not asserted, RX_ER has no effect.

 

 

 

 

 

 

 

 

 

PD[6]

V16

General-purpose I/O port D bit 6ÑThis is bit 6 of the general-purpose I/O port D.

 

 

 

RTS4

 

 

 

 

 

 

 

RTS4ÑActive low request to send output indicates that SCC4 is ready to transmit data.

 

 

 

MII_RX_DV

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MII receive data validÑWhen input signal RX_DV is asserted, the PHY is indicating that a

 

 

 

 

 

 

valid nibble is present on the MII. This signal shall remain asserted from the Þrst recovered

 

 

 

 

 

 

nibble of the frame through the last nibble. Assertion of RX_DV must start no later than the

 

 

 

 

 

 

SFD and exclude any EOF.

 

 

 

 

 

 

 

 

 

 

PD[5]

U15

General-purpose I/O port D bit 5ÑThis is bit 5 of the general-purpose I/O port D.

 

 

 

 

 

 

 

 

 

 

 

REJECT2

 

 

 

 

 

 

 

 

Reject 2ÑThis input to SCC2 allows a CAM to reject the current Ethernet frame after it

 

 

 

MII_TXD[3]

 

 

 

 

 

determines the frame address did not match.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MII transmit data 3ÑOutput signal TXD[3] represents bit 3 of the nibble of data when TX_EN

 

 

 

 

 

 

is asserted and has no meaning when TX_EN is negated.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2-2

 

 

MPC860T (Rev. D) Fast Ethernet Controller Supplement

MOTOROLA

 

 

 

 

 

PRELIMINARYÑSUBJECTFor ore nformationTO CHANGEOn ThisWITHOUTProduct,NOTICE

 

 

 

 

 

 

 

Go to: www.freescale.com

 

 

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Contents MPC860T Rev. D Fast Ethernet Controller Freescale Semiconductor, IncMotorola Literature Distribution Centers Contents Parallel I/O Ports Contents Paragraph Title Number Illustrations Title NumberViii MPC860T Rev. D Fast Ethernet Controller Supplement Tables Number Lists signiÞcant changes between revisions of this document Document Revision HistoryOverview Document Revision HistoryFeatures Comparison with the MPC8601 MPC860TBlock Diagram Embedded PowerPC Processor Core System Interface Unit SIUFast Ethernet Controller Glueless System Design SIU Interrupt ConÞgurationInc Signal Descriptions FEC Signal DescriptionsName Pin Description RXD3 L1RSYNCBMiimdc MiitxerREJECT4 REJECT3MIITXD2 MIITXD1Freescale Semiconductor, Inc Transceiver Connection MII SignalsSignal Description FEC Signal Name This chapter discusses the operation of the FECTXD0 Serial Mode Connections to the External TransceiverFEC Frame Transmission RXD0FEC Frame Reception FEC Command Set CAM InterfaceEthernet Address Recognition Hash Table Algorithm Rcntrlprom =Inter-Packet Gap Time Collision HandlingReception Errors Ethernet Error-Handling ProcedureTransmission Errors Internal and External LoopbackReception Errors Chapter Parallel I/O Ports Port D Pin FunctionsPort D Registers Enabling MII ModeSignal Function Shows the port D pin assignmentsSdma Registers CLKFRZ Faid RAID Describes Sdcr ÞeldsSdcr Field Descriptions BitsFEC Parameter RAM Memory Map Parameter RAMBrießy describes each enter in the FEC parameter RAM Address Name Description SectionRAM Perfect Match Address Low Register Addrlow Describes the Addrlow Þelds RAM Perfect Match Address High AddrhighRAM Hash Table High Hashtablehigh Describes the Addrhigh ÞeldsHashtablehigh Field Descriptions RAM Hash Table Low HashtablelowDescribes Hashtablehigh Þelds HashhighDescribes Hashtablelow Þelds Beginning of RxBD Ring RdesstartBeginning of TxBD Ring Xdesstart Describes Rdesstart ÞeldsReceive Buffer Size Register Rbuffsize Describes Xdesstart ÞeldsXdesstart Field Descriptions Describes Rbuffsize Þelds Spare Fecpin Etheren Reset MUXEthernet Control Register Ecntrl Rbuffsize Field DescriptionsEcntrl Field Descriptions Interrupt Event IEVENT/Interrupt Mask Register ImaskDescribes Ecntrl Þelds Fecpinmux10. IEVENT/IMASK Field Descriptions Ethernet Interrupt Vector Register IvecRfint to notify at the end of frame Hberr11. Ivec Field Descriptions RxBD Active Register Rdesactive11 describes Ivec Þelds IlevelTxBD Active Register Xdesactive 12 describes Rdesactive Þelds12. Rdesactive Field Descriptions MII Management Frame Register Miidata 13 describes Xdesactive Þelds13. Xdesactive Field Descriptions 14 describes Miidata Þelds 14. Miidata Field Descriptions15. Miispeed Field Descriptions MII Speed Control Register Miispeed15 describes Miispeed Þelds Dispreamble Miispeed16. Programming Examples for Miispeed Register Fifo Receive Bound Register Rbound17 describes Rbound Þelds 17. Rbound Field Descriptions18 describes Rñfstart Þelds Fifo Receive Start Register RfstartTransmit Watermark Register Xwmrk 18. Rfstart Field DescriptionsFifo Transmit Start Register Xfstart 19 bit Þeld descriptions for Xwmrk19. Xwmrk Field Descriptions 20. Xfstart Field Descriptions DMA Function Code Register Funcode20 describes Xfstart Þelds DATABO0 DATABO1 DESCBO0 DESCBO1 FC1 FC2 FC321. Funcode Field Descriptions Receive Control Register Rcntrl21 describes Funcode Þelds Descbo22. Rcntrl Field Descriptions Receive Hash Register Rhash22 describes Rcntrl Þelds Bcrej24 describes Xcntrl Þelds Transmit Control Register Xcntrl22 describes Rhash Þelds 23. Rhash Field DescriptionsHardware Initialization User Initialization before Setting EcntrletherenInitialization Sequence 25. Hardware InitializationUser Initialization after Asserting Ecntrletheren 27. User Initialization before Setting EcntrletherenDescriptor Controller Initialization Step DescriptionEthernet Receive Buffer Descriptor RxBD 27. User Initialization after Setting EcntrletherenBuffer Descriptors BDs StepRO1 RO2 Data Length RxBD format is shown in Table27. Receive Buffer Descriptor RxBD Field Description RO129. Transmit Buffer Descriptor TxBD Field Descriptions Ethernet Transmit Buffer Descriptor TxBD29 describes TxBD Þelds TO1 TO2 DEF CSLXcntrlhbc = DataFreescale Semiconductor, Inc MII Receive Signal Timing RXD30, RXDV, RXER, Rxclk DC Electrical CharacteristicsAC Electrical Characteristics Electrical SpeciÞcationsMII Transmit Signal Timing MII Transmit Signal Timing TXD30, TXEN, TXER, TxclkMII Receive Signal Timing Num Characteristic Min Max UnitTxen Txer MII Async Inputs Signal Timing CRS, COLMII Async Inputs Signal Timing CRS, COLShows the MII serial management channel timing diagram MII Serial Management Channel TimingFollowing pins are marked as spare on MPC860T Pin AssignmentsFreescale Semiconductor, Inc Freescale Semiconductor, Inc For More Information On This Product
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