Freescale Semiconductor MPC860T user manual Xcntrlhbc =, Data

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Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

Table 6-29. Transmit Buffer Descriptor (TxBD) Field Descriptions (Continued)

Bits

Name

 

Description

 

 

 

2

W

Wrap, written by user.

 

 

0 The next BD is found in the consecutive location

 

 

1 The next BD is found at the location deÞned in X_DES_START.

 

 

 

3

TO2

Transmit software ownership bit

 

 

This Þeld is available for use by software. This read/write bit is not modiÞed by hardware and its

 

 

value does not affect hardware.

 

 

 

4

L

Last in frame, written by user.

 

 

0

The buffer is not the last in the transmit frame.

 

 

1

The buffer is the last in the transmit frame.

 

 

 

5

TC

Tx CRC, written by user (valid if L = 1).

 

 

0 End transmission immediately after the last data byte.

 

 

1 Transmit the CRC sequence after the last data byte.

 

 

 

6

DEF

Defer indication, written by FEC (valid if L = 1). Set when the FEC had to defer while trying to

 

 

transmit a frame. This bit is not set if a collision occurs during transmission.

 

 

 

7

HB

Heartbeat error, written by FEC (valid if L = 1). Set to indicate that the collision input was not

 

 

asserted within the heartbeat window after transmission completed. HB can be set only if

 

 

X_CNTRL[HBC] = 1.

 

 

 

8

LC

Late collision, written by FEC (valid if L = 1). Set to indicate that a collision occurred after 56 data

 

 

bytes were transmitted. The FEC terminates the transmission.

 

 

 

9

RL

Retransmission limit, written by FEC (valid if L = 1). Set to indicate that the transmitter failed retry

 

 

limit + 1 attempts to send a message due to repeated collisions.

 

 

 

10Ð13

RC

Retry count, written by FEC (valid if L = 1). Counts retries needed to successfully send this

 

 

frame. If RC = 0, the frame was sent correctly the Þrst time. If RC = 15, the frame was sent

 

 

successfully while the retry count was at its maximum value. If RL = 1, RC has no meaning.

 

 

 

14

UN

Underrun, written by FEC (valid if L = 1). If set, the FEC encountered a transmit FIFO underrun

 

 

while sending one or more buffers associated with this frame. When a Tx FIFO underrun occurs,

 

 

transmission of the frame stops and an incorrect CRC is appended. Any remaining buffers

 

 

associated with this frame are accessed and dumped by the transmit logic.

 

 

 

15

CSL

Carrier sense lost, written by FEC (valid if L = 1). Carrier sense dropped out or never asserted

 

 

during transmission of a frame without collision.

 

 

 

Offset+2

Data

Data length, written by user and never by the FEC. Indicates the number of octets the FEC

 

length

should send from this BDÕs buffer. The DMA engine uses bits 21Ð31. Bits 16Ð20 are ignored.

 

 

 

Offset+4

Tx

Tx buffer pointer A[0Ð31], written by user and never by the FEC. The transmit buffer pointer,

 

buffer

which contains the address of the associated buffer, may be even or odd. The buffer must reside

 

pointer

in external memory to the MPC860T.

 

 

 

 

On transmit, an underrun occurs if the transmit FIFO empties of data before the end of the frame. In this case, a bad CRC is appended to the partially transmitted data. In addition, the UN bit is set in the last BD in the current frame. This situation can occur if the FEC cannot access the 60x bus or if the next BD in the frame is unavailable.

Note: A software driver that sets TxBD[R] should then write to X_DES_ACTIVE.

MOTOROLAChapter 6.Programming Model6-27

PRELIMINARYÑSUBJECTFor ore nformationTO CHANGEOn ThisWITHOUTProduct,NOTICE

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Contents Freescale Semiconductor, Inc MPC860T Rev. D Fast Ethernet ControllerMotorola Literature Distribution Centers Contents Parallel I/O Ports Contents Paragraph Title Number Title Number IllustrationsViii MPC860T Rev. D Fast Ethernet Controller Supplement Tables Number Document Revision History Document Revision HistoryOverview Lists signiÞcant changes between revisions of this documentComparison with the MPC860 Features1 MPC860TBlock Diagram Fast Ethernet Controller Embedded PowerPC Processor CoreSystem Interface Unit SIU SIU Interrupt ConÞguration Glueless System DesignInc Name Pin Description Signal DescriptionsFEC Signal Descriptions Miitxer L1RSYNCBMiimdc RXD3MIITXD1 REJECT3MIITXD2 REJECT4Freescale Semiconductor, Inc This chapter discusses the operation of the FEC MII SignalsSignal Description FEC Signal Name Transceiver ConnectionRXD0 Serial Mode Connections to the External TransceiverFEC Frame Transmission TXD0FEC Frame Reception Ethernet Address Recognition FEC Command SetCAM Interface Rcntrlprom = Hash Table AlgorithmCollision Handling Inter-Packet Gap TimeInternal and External Loopback Ethernet Error-Handling ProcedureTransmission Errors Reception ErrorsReception Errors Port D Pin Functions Chapter Parallel I/O PortsShows the port D pin assignments Enabling MII ModeSignal Function Port D RegistersCLK Sdma RegistersBits Describes Sdcr ÞeldsSdcr Field Descriptions FRZ Faid RAIDAddress Name Description Section Parameter RAMBrießy describes each enter in the FEC parameter RAM FEC Parameter RAM Memory MapRAM Perfect Match Address Low Register Addrlow Describes the Addrhigh Þelds RAM Perfect Match Address High AddrhighRAM Hash Table High Hashtablehigh Describes the Addrlow ÞeldsHashhigh RAM Hash Table Low HashtablelowDescribes Hashtablehigh Þelds Hashtablehigh Field DescriptionsDescribes Rdesstart Þelds Beginning of RxBD Ring RdesstartBeginning of TxBD Ring Xdesstart Describes Hashtablelow ÞeldsXdesstart Field Descriptions Receive Buffer Size Register RbuffsizeDescribes Xdesstart Þelds Rbuffsize Field Descriptions Spare Fecpin Etheren Reset MUXEthernet Control Register Ecntrl Describes Rbuffsize ÞeldsFecpinmux Interrupt Event IEVENT/Interrupt Mask Register ImaskDescribes Ecntrl Þelds Ecntrl Field DescriptionsHberr Ethernet Interrupt Vector Register IvecRfint to notify at the end of frame 10. IEVENT/IMASK Field DescriptionsIlevel RxBD Active Register Rdesactive11 describes Ivec Þelds 11. Ivec Field Descriptions12. Rdesactive Field Descriptions TxBD Active Register Xdesactive12 describes Rdesactive Þelds 13. Xdesactive Field Descriptions MII Management Frame Register Miidata13 describes Xdesactive Þelds 14. Miidata Field Descriptions 14 describes Miidata ÞeldsDispreamble Miispeed MII Speed Control Register Miispeed15 describes Miispeed Þelds 15. Miispeed Field Descriptions17. Rbound Field Descriptions Fifo Receive Bound Register Rbound17 describes Rbound Þelds 16. Programming Examples for Miispeed Register18. Rfstart Field Descriptions Fifo Receive Start Register RfstartTransmit Watermark Register Xwmrk 18 describes Rñfstart Þelds19. Xwmrk Field Descriptions Fifo Transmit Start Register Xfstart19 bit Þeld descriptions for Xwmrk DATABO0 DATABO1 DESCBO0 DESCBO1 FC1 FC2 FC3 DMA Function Code Register Funcode20 describes Xfstart Þelds 20. Xfstart Field DescriptionsDescbo Receive Control Register Rcntrl21 describes Funcode Þelds 21. Funcode Field DescriptionsBcrej Receive Hash Register Rhash22 describes Rcntrl Þelds 22. Rcntrl Field Descriptions23. Rhash Field Descriptions Transmit Control Register Xcntrl22 describes Rhash Þelds 24 describes Xcntrl Þelds25. Hardware Initialization User Initialization before Setting EcntrletherenInitialization Sequence Hardware InitializationStep Description 27. User Initialization before Setting EcntrletherenDescriptor Controller Initialization User Initialization after Asserting EcntrletherenStep 27. User Initialization after Setting EcntrletherenBuffer Descriptors BDs Ethernet Receive Buffer Descriptor RxBDRO1 RxBD format is shown in Table27. Receive Buffer Descriptor RxBD Field Description RO1 RO2 Data LengthTO1 TO2 DEF CSL Ethernet Transmit Buffer Descriptor TxBD29 describes TxBD Þelds 29. Transmit Buffer Descriptor TxBD Field DescriptionsData Xcntrlhbc =Freescale Semiconductor, Inc Electrical SpeciÞcations DC Electrical CharacteristicsAC Electrical Characteristics MII Receive Signal Timing RXD30, RXDV, RXER, RxclkNum Characteristic Min Max Unit MII Transmit Signal Timing TXD30, TXEN, TXER, TxclkMII Receive Signal Timing MII Transmit Signal TimingCRS, COL MII Async Inputs Signal Timing CRS, COLMII Async Inputs Signal Timing Txen TxerMII Serial Management Channel Timing Shows the MII serial management channel timing diagramMPC860T Pin Assignments Following pins are marked as spare onFreescale Semiconductor, Inc Freescale Semiconductor, Inc For More Information On This Product
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