Cypress CY7C1382F, CY7C1380F, CY7C1380D, CY7C1382D manual Truth Table, Operation Add. Used

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CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

Truth Table

The Truth Table for this data sheet follows.[4, 5, 6, 7, 8]

Operation

Add. Used

 

CE1

CE2

 

CE3

ZZ

 

ADSP

 

ADSC

 

ADV

 

 

WRITE

 

OE

 

CLK

DQ

Deselect Cycle, Power Down

None

 

H

X

 

X

L

 

X

 

L

 

X

 

 

X

 

X

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselect Cycle, Power Down

None

 

L

L

 

X

L

 

L

 

X

 

X

 

 

X

 

X

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselect Cycle, Power Down

None

 

L

X

 

H

L

 

L

 

X

 

X

 

 

X

 

X

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselect Cycle, Power Down

None

 

L

L

 

X

L

 

H

 

L

 

X

 

 

X

 

X

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselect Cycle, Power Down

None

 

L

X

 

H

L

 

H

 

L

 

X

 

 

X

 

X

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Sleep Mode, Power Down

None

 

X

X

 

X

H

 

X

 

X

 

X

 

 

X

 

X

 

X

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READ Cycle, Begin Burst

External

 

L

H

 

L

L

 

L

 

X

 

X

 

 

X

 

L

 

L-H

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READ Cycle, Begin Burst

External

 

L

H

 

L

L

 

L

 

X

 

X

 

 

X

 

H

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WRITE Cycle, Begin Burst

External

 

L

H

 

L

L

 

H

 

L

 

X

 

 

L

 

X

 

L-H

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READ Cycle, Begin Burst

External

 

L

H

 

L

L

 

H

 

L

 

X

 

 

H

 

L

 

L-H

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READ Cycle, Begin Burst

External

 

L

H

 

L

L

 

H

 

L

 

X

 

 

H

 

H

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READ Cycle, Continue Burst

Next

 

X

X

 

X

L

 

H

 

H

 

L

 

 

H

 

L

 

L-H

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READ Cycle, Continue Burst

Next

 

X

X

 

X

L

 

H

 

H

 

L

 

 

H

 

H

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READ Cycle, Continue Burst

Next

 

H

X

 

X

L

 

X

 

H

 

L

 

 

H

 

L

 

L-H

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READ Cycle, Continue Burst

Next

 

H

X

 

X

L

 

X

 

H

 

L

 

 

H

 

H

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WRITE Cycle, Continue Burst

Next

 

X

X

 

X

L

 

H

 

H

 

L

 

 

L

 

X

 

L-H

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WRITE Cycle, Continue Burst

Next

 

H

X

 

X

L

 

X

 

H

 

L

 

 

L

 

X

 

L-H

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READ Cycle, Suspend Burst

Current

 

X

X

 

X

L

 

H

 

H

 

H

 

 

H

 

L

 

L-H

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READ Cycle, Suspend Burst

Current

 

X

X

 

X

L

 

H

 

H

 

H

 

 

H

 

H

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READ Cycle, Suspend Burst

Current

 

H

X

 

X

L

 

X

 

H

 

H

 

 

H

 

L

 

L-H

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READ Cycle, Suspend Burst

Current

 

H

X

 

X

L

 

X

 

H

 

H

 

 

H

 

H

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WRITE Cycle, Suspend Burst

Current

 

X

X

 

X

L

 

H

 

H

 

H

 

 

L

 

X

 

L-H

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WRITE Cycle, Suspend Burst

Current

 

H

X

 

X

L

 

X

 

H

 

H

 

 

L

 

X

 

L-H

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes

4.X = Don't Care, H = Logic HIGH, L = Logic LOW.

5.WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.

6.The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

7.The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the write cycle.

8.OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).

Document #: 38-05543 Rev. *F

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Contents Selection Guide FeaturesFunctional Description Description 250 MHz 200 MHz 167 MHz UnitLogic Block Diagram CY7C1380D/CY7C1380F 3 512K x Logic Block Diagram CY7C1382D/CY7C1382F 3 1M xPin Configurations Pin Tqfp Pinout 3-Chip EnableBall BGA Pinout Ball Fbga Pinout 3-Chip Enable Pin Definitions Name Description Power supply inputs to the core of the devicePower supply for the I/O circuitry Ground for the core of the device TMS Pin Definitions TCK Jtag Single Write Accesses Initiated by Adsc Single Write Accesses Initiated by AdspSingle Read Accesses Functional OverviewAddress Sleep ModeBurst Sequences A1 A0 Parameter Description Test Conditions MinTruth Table Operation Add. UsedFunction CY7C1380D/CY7C1380F Truth Table for Read/Write 4Function CY7C1382D/CY7C1382F TAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Bypass RegisterParameter Description Min TAP TimingReserved Clock5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions Parameter Description Test Conditions MinIdentification Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBall BGA Boundary Scan Order 14 Bit # Ball IDA10 B10 P10 Operating Range Electrical Characteristics Over the Operating RangeMaximum Ratings Range AmbientPackage CapacitanceThermal Resistance EIA/JESD51AC Test Loads and Waveforms 3V I/O Test Load 5V I/O Test LoadSetup Times Switching Characteristics Over the Operating Range 20Output Times Switching Waveforms Read Cycle TimingWrite Cycle Timing 26 Read/Write Cycle Timing 26, 28 ZZ Mode Timing 30 Ordering Information 200 167 Package Diagrams Pin Thin Plastic Quad Flat Pack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Submission Orig. Description of Change DateWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB
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