Cypress CY7C1380D, CY7C1380F, CY7C1382F, CY7C1382D manual Read/Write Cycle Timing 26, 28

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CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

Switching Waveforms (continued)

Figure 12. Read/Write Cycle Timing [26, 28, 29]

tCYC

CLK

tCH

tCL

	tADS	tADH
ADSP
ADSC
	tAS	tAH
ADDRESS	A1	A2
BWE,
BW X
	tCES	tCEH
CE

ADV

tCO

A3	A4
tWES	tWEH

tDS tDH

Data In (D)		High-Z

t	tOEHZ
CLZ

D(A3)

tOELZ

D(A5) D(A6)

Data Out (Q)	High-Z	Q(A1)	Q(A2)	Q(A4)	Q(A4+1)	Q(A4+2)	Q(A4+3)
		Back-to-Back READs	Single WRITE		BURST READ

Back-to-Back

WRITEs

DON’T CARE

UNDEFINED

Notes

28.The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.

29.GW is HIGH.

Document #: 38-05543 Rev. *F

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Contents Functional Description FeaturesSelection Guide Description 250 MHz 200 MHz 167 MHz UnitLogic Block Diagram CY7C1382D/CY7C1382F 3 1M x Logic Block Diagram CY7C1380D/CY7C1380F 3 512K xPin Tqfp Pinout 3-Chip Enable Pin ConfigurationsBall BGA Pinout Ball Fbga Pinout 3-Chip Enable Power supply for the I/O circuitry Power supply inputs to the core of the devicePin Definitions Name Description Ground for the core of the deviceTMS Pin DefinitionsTCK Jtag Single Read Accesses Single Write Accesses Initiated by AdspSingle Write Accesses Initiated by Adsc Functional OverviewBurst Sequences Sleep ModeAddress A1 A0 Parameter Description Test Conditions MinOperation Add. Used Truth TableFunction CY7C1380D/CY7C1380F Truth Table for Read/Write 4Function CY7C1382D/CY7C1382F TAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag Bypass Register TAP Instruction SetReserved TAP TimingParameter Description Min Clock3V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Parameter Description Test Conditions MinScan Register Sizes Identification Register DefinitionsIdentification Codes Register Name Bit SizeBit # Ball ID Ball BGA Boundary Scan Order 14A10 B10 P10 Maximum Ratings Electrical Characteristics Over the Operating RangeOperating Range Range AmbientThermal Resistance CapacitancePackage EIA/JESD515V I/O Test Load AC Test Loads and Waveforms 3V I/O Test Load Setup Times Switching Characteristics Over the Operating Range 20 Output Times Read Cycle Timing Switching WaveformsWrite Cycle Timing 26 Read/Write Cycle Timing 26, 28 ZZ Mode Timing 30 Ordering Information 200 167 Pin Thin Plastic Quad Flat Pack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Submission Orig. Description of Change Date Document HistoryWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB

Switching Waveforms (continued)

Figure 12. Read/Write Cycle Timing [26, 28, 29]

ADV

CLZ