Cypress CY7C1380F, CY7C1380D, CY7C1382F, CY7C1382D manual Ball BGA Pinout

Page 4

CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

119-Ball BGA Pinout

Figure 3. CY7C1380F (512K X 36)

1

2

3

4

5

6

7

A

VDDQ

A

A

A

A

VDDQ

ADSP

B

NC/288M

A

A

A

A

NC/576M

ADSC

C

NC/144M

A

A

VDD

A

A

NC/1G

D

DQC

DQPC

VSS

NC

VSS

DQPB

DQB

E

DQC

DQC

VSS

1

VSS

DQB

DQB

CE

F

VDDQ

DQC

VSS

VSS

DQB

VDDQ

OE

G

DQC

DQC

C

B

DQB

DQB

BW

ADV

BW

H

DQC

DQC

VSS

VSS

DQB

DQB

GW

J

VDDQ

VDD

NC

VDD

NC

VDD

VDDQ

K

DQD

DQD

VSS

CLK

VSS

DQA

DQA

L

DQD

DQD

D

NC

A

DQA

DQA

BW

BW

M

VDDQ

DQD

VSS

VSS

DQA

VDDQ

BWE

N

DQD

DQD

VSS

A1

VSS

DQA

DQA

P

DQD

DQPD

VSS

A0

VSS

DQPA

DQA

R

NC

A

MODE

VDD

NC

A

NC

T

NC

NC/72M

A

A

A

NC/36M

ZZ

U

VDDQ

TMS

TDI

TCK

TDO

NC

VDDQ

Figure 4. CY7C1382F (1M X 18)

1

2

3

4

5

6

7

A

VDDQ

A

A

A

A

VDDQ

ADSP

B

NC/288M

A

A

A

A

NC/576M

ADSC

C

NC/144M

A

A

VDD

A

A

NC/1G

D

DQB

NC

VSS

NC

VSS

DQPA

NC

E

NC

DQB

VSS

1

VSS

NC

DQA

CE

F

VDDQ

NC

VSS

VSS

DQA

VDDQ

OE

G

NC

DQB

B

NC

NC

DQA

BW

ADV

H

DQB

NC

VSS

VSS

DQA

NC

GW

J

VDDQ

VDD

NC

VDD

NC

VDD

VDDQ

K

NC

DQB

VSS

CLK

VSS

NC

DQA

L

DQB

NC

NC

NC

A

DQA

NC

BW

M

VDDQ

DQB

VSS

VSS

NC

VDDQ

BWE

N

DQB

NC

VSS

A1

VSS

DQA

NC

P

NC

DQPB

VSS

A0

VSS

NC

DQA

R

NC

A

MODE

VDD

NC

A

NC

T

NC/72M

A

A

NC/36M

A

A

ZZ

U

VDDQ

TMS

TDI

TCK

TDO

NC

VDDQ

Document #: 38-05543 Rev. *F

Page 4 of 34

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Contents Features Functional DescriptionSelection Guide Description 250 MHz 200 MHz 167 MHz UnitLogic Block Diagram CY7C1380D/CY7C1380F 3 512K x Logic Block Diagram CY7C1382D/CY7C1382F 3 1M xPin Configurations Pin Tqfp Pinout 3-Chip EnableBall BGA Pinout Ball Fbga Pinout 3-Chip Enable Power supply inputs to the core of the device Power supply for the I/O circuitryPin Definitions Name Description Ground for the core of the deviceTMS Pin DefinitionsTCK Jtag Single Write Accesses Initiated by Adsp Single Read AccessesSingle Write Accesses Initiated by Adsc Functional OverviewSleep Mode Burst SequencesAddress A1 A0 Parameter Description Test Conditions MinTruth Table Operation Add. UsedFunction CY7C1380D/CY7C1380F Truth Table for Read/Write 4Function CY7C1382D/CY7C1382F TAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Bypass RegisterTAP Timing ReservedParameter Description Min ClockTAP DC Electrical Characteristics And Operating Conditions 3V TAP AC Test Conditions5V TAP AC Test Conditions Parameter Description Test Conditions MinIdentification Register Definitions Scan Register SizesIdentification Codes Register Name Bit SizeBall BGA Boundary Scan Order 14 Bit # Ball IDA10 B10 P10 Electrical Characteristics Over the Operating Range Maximum RatingsOperating Range Range AmbientCapacitance Thermal ResistancePackage EIA/JESD51AC Test Loads and Waveforms 3V I/O Test Load 5V I/O Test LoadSetup Times Switching Characteristics Over the Operating Range 20Output Times Switching Waveforms Read Cycle TimingWrite Cycle Timing 26 Read/Write Cycle Timing 26, 28 ZZ Mode Timing 30 Ordering Information 200 167 Package Diagrams Pin Thin Plastic Quad Flat Pack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Submission Orig. Description of Change DateWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB