Cypress CY7C1382F, CY7C1380F, CY7C1380D, CY7C1382D Sales, Solutions, and Legal Information, Usb

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CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

Products

 

PSoC Solutions

 

PSoC

psoc.cypress.com

General

psoc.cypress.com/solutions

Clocks & Buffers

clocks.cypress.com

Low Power/Low Voltage

psoc.cypress.com/low-power

Wireless

wireless.cypress.com

Precision Analog

psoc.cypress.com/precision-analog

Memories

memory.cypress.com

LCD Drive

psoc.cypress.com/lcd-drive

Image Sensors

image.cypress.com

CAN 2.0b

psoc.cypress.com/can

 

 

USB

psoc.cypress.com/usb

© Cypress Semiconductor Corporation, 2006-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document #: 38-05543 Rev. *F

Revised January 12, 2009

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All products and company names mentioned in this document may be the trademarks of their respective holders.

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Contents Selection Guide FeaturesFunctional Description Description 250 MHz 200 MHz 167 MHz UnitLogic Block Diagram CY7C1380D/CY7C1380F 3 512K x Logic Block Diagram CY7C1382D/CY7C1382F 3 1M xPin Configurations Pin Tqfp Pinout 3-Chip EnableBall BGA Pinout Ball Fbga Pinout 3-Chip Enable Pin Definitions Name Description Power supply inputs to the core of the devicePower supply for the I/O circuitry Ground for the core of the deviceTMS Pin DefinitionsTCK Jtag Single Write Accesses Initiated by Adsc Single Write Accesses Initiated by AdspSingle Read Accesses Functional OverviewAddress Sleep ModeBurst Sequences A1 A0 Parameter Description Test Conditions MinTruth Table Operation Add. UsedFunction CY7C1380D/CY7C1380F Truth Table for Read/Write 4Function CY7C1382D/CY7C1382F TAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Bypass RegisterParameter Description Min TAP TimingReserved Clock5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions Parameter Description Test Conditions MinIdentification Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBall BGA Boundary Scan Order 14 Bit # Ball IDA10 B10 P10 Operating Range Electrical Characteristics Over the Operating RangeMaximum Ratings Range AmbientPackage CapacitanceThermal Resistance EIA/JESD51AC Test Loads and Waveforms 3V I/O Test Load 5V I/O Test LoadSetup Times Switching Characteristics Over the Operating Range 20Output Times Switching Waveforms Read Cycle TimingWrite Cycle Timing 26 Read/Write Cycle Timing 26, 28 ZZ Mode Timing 30 Ordering Information 200 167 Package Diagrams Pin Thin Plastic Quad Flat Pack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Submission Orig. Description of Change DateWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB