Cypress CY7C1382D, CY7C1380F, CY7C1380D, CY7C1382F manual Switching Waveforms, Read Cycle Timing

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CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

Switching Waveforms

Figure 10. Read Cycle Timing [26]

CLK

ADSP

ADSC

tCYC

tCH

tCL

tADS tADH

tAS tAH

ADDRESS

GW, BWE, BWx

ADV

Data Out (Q)

tWES tWEH

tCES tCEH

tCLZ

High-Z tCO

tADVS tADVH

tOEV

tOEHZ	t	OELZ
		OELZ

Q(A1)

tCO

tDOH

Q(A2)

Burst continued with new base address

Deselect cycle

ADV suspends burst.

tCHZ

Q(A2 + 1)

Q(A2 + 2)

Q(A2 + 3)

Q(A2)

Q(A2 + 1)

Burst wraps around to its initial state

Single READ

BURST READ

DON’T CARE

UNDEFINED

Note

26. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

Document #: 38-05543 Rev. *F

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Contents Description 250 MHz 200 MHz 167 MHz Unit FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1382D/CY7C1382F 3 1M x Logic Block Diagram CY7C1380D/CY7C1380F 3 512K xPin Tqfp Pinout 3-Chip Enable Pin ConfigurationsBall BGA Pinout Ball Fbga Pinout 3-Chip Enable Ground for the core of the device Power supply inputs to the core of the devicePower supply for the I/O circuitry Pin Definitions Name DescriptionTCK Jtag Pin DefinitionsTMS Functional Overview Single Write Accesses Initiated by AdspSingle Read Accesses Single Write Accesses Initiated by AdscA1 A0 Parameter Description Test Conditions Min Sleep ModeBurst Sequences AddressOperation Add. Used Truth TableFunction CY7C1382D/CY7C1382F Truth Table for Read/Write 4Function CY7C1380D/CY7C1380F Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Controller Block Diagram Bypass Register TAP Instruction SetClock TAP TimingReserved Parameter Description MinParameter Description Test Conditions Min TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions 5V TAP AC Test ConditionsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Identification CodesBit # Ball ID Ball BGA Boundary Scan Order 14A10 B10 P10 Range Ambient Electrical Characteristics Over the Operating RangeMaximum Ratings Operating RangeEIA/JESD51 CapacitanceThermal Resistance Package5V I/O Test Load AC Test Loads and Waveforms 3V I/O Test LoadOutput Times Switching Characteristics Over the Operating Range 20Setup Times Read Cycle Timing Switching WaveformsWrite Cycle Timing 26 Read/Write Cycle Timing 26, 28 ZZ Mode Timing 30 Ordering Information 200 167 Pin Thin Plastic Quad Flat Pack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Submission Orig. Description of Change Date Document HistoryUSB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions